TMC22071A 查看數據表（PDF） - Fairchild Semiconductor

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产品描述 (功能)

比赛名单

TMC22071A

Genlocking Video Digitizer

Fairchild Semiconductor 

TMC22071A

0

78

15 16

000

00

PRODUCT SPECIFICATION

23

24

31 32

39 40

0001

00000

46

00

STATUS REGISTER

47

54 55

58

65-22071-06

Figure 4. Control Register Map

Control Register Bit Functions

Bit

0

1-3

4-6

7,8

9

10-11

12-16

17-24

Name

SRESET

FORMAT

TEST

SOURCE

VGAIN

TEST

SUBPIX

LEADLAG

Function

Software reset. When LOW, resets and holds internal state machines, resets Control

Register with previously written values, and disables output drivers. When HIGH,

SRESET starts and runs state machines, PXCK, and enables outputs.

Input signal format select.

Bit 3 is the MSB.

000 NTSC at 12.27 Mpps.

001 NTSC at 13.5 Mpps.

010 Reserved.

011 Reserved.

100 PAL at 13.5 Mpps.

101 Reserved.

11x Reserved.

Factory test control bits. These should be set LOW.

Video source select. Bit 8 is the MSB.

00 VIN1

01 VIN2

1x VIN3

Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X.

Factory test control bits. These should be set LOW.

These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by

-16/32 to +15/32 pixels. Bit 16 is the two’s complement MSB. When SUBPIX is 00h,

HSYNC and incoming video are subject to LEADLAG. A value of 18h delays HSYNC

1/4 pixel. A value of 08h advances HSYNC 1/4 pixel.

This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV

cycles. When LEADLAG is 7Bh, HSYNC and incoming video are in alignment. A value of

83h delays HSYNC eight LDV cycles. A value of 73h advances HSYNC eight LDV

cycles. Bit 24 is the MSB.

8

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