MX86251
DRAM Interface Pins: (Continued)
Pin Name Pin No. Type
CAS1# 81
TO
CAS2# 80
TO
CAS3# 79
TO
CAS4#
101
TO
CAS5#
102
TO
CAS6# 103
TO
Description
For dual CAS DRAM type configuration, this output is CAS1#. It is the CAS
address strobe of byte lane 1.
For dual WE DRAM type configuration, this output is WE1#, it is the WE# control
signal of byte lane 1.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
For dual CAS DRAM type configuration, this output is CAS2#. It is the CAS
address strobe of byte lane 2.
For dual WE DRAM type configuration, this output is WE2#, it is the WE# control
signal of byte lane 2.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
For dual CAS DRAM type configuration, this output is CAS3#. It is the CAS
address strobe of byte lane 3.
For dual WE DRAM type configuration, this output is WE3#, it is the WE#
control signal of byte lane 3.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
For dual CAS DRAM type configuration, this output is CAS4#. It is the CAS
address strobe of byte lane 4.
For dual WE DRAM type configuration, this output is WE4#, it is the WE#
control signal of byte lane 4.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
For dual CAS DRAM type configuration, this output is CAS5#. It is the CAS
address strobe of byte lane 5.
For dual WE DRAM type configuration, this output is WE5#, it is the WE#
control signal of byte lane 5.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
For dual CAS DRAM type configuration, this output is CAS6#. It is the CAS
address strobe of byte lane 6.
For dual WE DRAM type configuration, this output is WE6#, it is the WE#
control signal of byte lane 6.
In PUMA interface, this output will be tristated if GUI is not granted to access the
memory bus.
P/N:PM0476
REV. 1.2 , FEB 11, 1998
14