MX86251 查看數據表（PDF） - Macronix International

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MX86251

3D graphic chipset

Macronix International 

MX86251

Media Port and Feature Connector Related Interface Pins:

Pin Name

P0

P1

P2

P3

P4

P5

P6

P7

Pin No. Type

141

IO

142

143

144

145

146

147

148

P8

187

IO

P9

188

IO

P10

190

IO

P11

191

IO

PCLK

150

IO

PENFEAT# 151

I

Description

P[7:0] is the pixel or video data bus from/to external Feature Connector or Video

Module Interfaces.

For 8-bit Feature Connector, this is a bi-directional pixel data bus. When

PENFEATL is low, it functions as inputs. The pixel data from external display or

video card will be passed to the internal RAMDAC for display. If PENFEATL

is high, the internal RAMDAC uses pixel data internally generated for display.

In this case, if PA output control for DPMS, which is defined in bit 3 of register

3?5/26, is set to normal operation, GUI will drive out pixel data. Otherwise, it will

tristate the output.

If VMI is used, P[7:0] is the video data inputs.

This chip supports SAA7110 video decoder and CL480 MPEG decoder

interfaces. For SAA7110 interfaces, P[7:0] is the lower byte of the 16-bit video

data inputs. For CL480 interfaces, it’s the 8-bit video data inputs.

P[15:8] is the pixel data bus from/to external Feature Connector or host data

bus from/to VMI.

If VMI is used, P(15:8) is used as the host data bus, which is bi-directional.

Through this bus, CPU can access the VMI module.

For SAA7110 interfaces, P(15:8) is the higher byte of the 16-bit video data

inputs. For CL480, it‘s the 8-bit host data bus, which is inputs in read cycles,

and outputs in write cycles.

Otherwise, P(15:8) functions as pixel output or video input. When PENFEATL is

low, it is used for video input, which will be passed to the internal RAMDAC for

display . If PENFEATL is high, the internally generated pixel data will be driven

out to video card if PA output control for DPMS is set to normal operation.

This is the pixel clock input/output pin.

For 8-bit Feature Connector, it's an input when PENFEATL# is low. In this case,

it is used for internal RAMDAC display. When PENFEATL# is high, the internally

generated pixel clock is driven out through this pin.

For VMI connection, PCLK is always put in tri-state. RAMDAC use internal pixel

clock for display.

If external DCLK is used, only 8-bit Feature Connector configuration is allowed,

i.e. other video interfaces are not applicable.

This is the EVIDEO# pin used as bidirection control for 8-bit Feature Connector.

When set to 1, GUI will drive P[15:0], BLANK#, HSYNC, VSYNC and PCLK to

the Feature Connector. When set to 0, all of these signal pins are tri-stated.

If video interface is enabled, i.e. either SAA7110 or CL480 is used for video data

input, this pin loses its function.

P/N:PM0476

REV. 1.2 , FEB 11, 1998

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