DRAIN SUPPLY
Vd = +4V
10µF
L
10,000pF
RF IN
L
100pF
L
MMIC CHIP
L
100pF
L
L
100pF
L
L
100pF
L
RF OUT
GROUND
(Back of Chip)
L
100pF
L = BOND WIRE INDUCTANCE
GATE SUPPLY
Vg
Figure 3. Recommended Application Schematic Circuit Diagram
Vdd (POSITIVE)
10µF
10, 00 0pF
10 0pF
5 MIL THICK
ALUMINA
50Ω
RF INPUT
10 0pF
10 0pF
DIE-ATTACH
80Au/20Sn
10 0pF
5 MIL THICK
ALUMINA
50Ω
RF OUTPUT
10 0pF
2 MIL GAP
Vg (NEGATIVE)
L < 0.015"
Note:
(4 Places)
Use 0.003" by 0.0005" Gold Ribbon for bonding. RF input and output bonds should be less than 0.015" long with stress relief.
Figure 4. Recommended Assembly Diagram
©2004 Fairchild Semiconductor Corporation
RMWP26001 Rev. C