TC70 查看數據表（PDF） - TelCom Semiconductor Inc => Microchip
零件编号
产品描述 (功能)
比赛名单
TC70
TelCom Semiconductor Inc => Microchip
TC70 Datasheet PDF : 7 Pages
| |||
TC70
TC71
MICROMASTER™ – SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
PIN DESCRIPTION
Pin No
(TC70)
1
Pin No
(TC71)
1
2
2
3
3
4
–
–
4
5
–
–
5
Symbol
VCCO
VCC
GND
CEI
TDI
CEO
TDO
6
–
WDD
–
6
PF
7
7
RS
8
8
VBATT
Description
VCC Output. The higher of VCC or VBATT is internally switched to this output.
Connect to VCC if VBATT and VCCO are not used.
VCC Input. +5V power supply.
GND Input. Ground.
Chip enable input. Chip enable to static RAM or other device to be battery
backed-up. Connect to ground if VCCO is not used.
Threshold detector input. When the voltage on threshold detector input (TDI) is
less than 1.3V, threshold detector output (TDO) goes low.
Chip enable output. This line goes low only when CEI is low and VCC is above
the RESET threshold.
Threshold detector output. TDO goes low when TDI is less than 1.3V and VCC is
greater than VBATT. (The threshold detector is turned off when VCC is less than
VBATT.
Watchdog disable input. Grounding this line disables the watchdog timer (no
RESET pulses are generated after the watchdog timer times out). This input is
provided to facilitate system debug. This input is internally pulled-up and can be
left open, or tied to VCC for normal watchdog operation.
Power fail output. This line goes low when VCC is below 4.5V nominal. It is used
to write-protect the external device to be battery backed.
RESET/STORE (Bidirectional). An open drain with pull-up (in output mode) that
goes active if:
1. VCC falls below 4.5V nominal
2. If pulled low by an external electronic signal or switch closure
3. If the watchdog is not strobed within the minimum watchdog timeout period
4. During power-up and power down
In the input mode, RS is a negative edge triggered input that resets the
watchdog timer when pulled to ground through a 10kΩ, 5% tolerance resistor.
Backup battery input. Connect to ground if battery backup is not used.
DETAILED DESCRIPTION
Precision Power Supply Monitor
The RS pin is immediately driven low any time VCC is
below 4.5V nominal. The processor is held in its reset state
during power-up and power-down. RS remains low for a
minimum of 500msec after VCC is within tolerance to allow
the power supply and processor to stabilize.
Watchdog Timer
The processor drives the RS pin with an input/output
(I/O) line in series with a voltage divider to VDD. Pulling the
bottom of this divider low results in an internal voltage
change (strobe) sufficient to reset the watchdog timer, but
above the VIL input threshold of the processor RESET input.
The processor must continuously apply strobes in this
manner within a set period to verify proper software execu-
tion. A momentary reset (500msec minimum) is generated
if a hardware or software failure keeps RS from being
strobed within the watchdog timeout period. This action
typically initiates the processor's power-up routine. If the
interruption persists, new reset pulses are generated each
timeout period until RS is strobed. The timeout period is
typically 700msec.
It is often difficult to debug a system while the watchdog
is continuously generating reset pulses. For example, the
watchdog must be disabled when the system is operated
with an in-circuit emulator (ICE). The watchdog disable input
(TC70) is provided for system debugging, (or if the watchdog
timer on-board the processor is to be used). Grounding
WDD disables the watchdog (all other functions remain
intact). For normal watchdog operation, WDD can be tied to
VDD.
The software routine that drives the RS strobe must be
in a section of the program that executes frequently enough
so the time between toggles is less than one watchdog
timeout period. The strobe signal can be derived from
microprocessor address, data and/or control signals. Typi-
cal circuit examples are shown in Figure 1.
5-10
TELCOM SEMICONDUCTOR, INC.
Share Link: