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TC70

MICROMASTER™ – SYSTEM SUPERVISOR WITH POWER SUPPLY MONITOR, WATCHDOG AND BATTERY BACKUP

TelCom Semiconductor Inc => Microchip 

MICROMASTER™ – SYSTEM SUPERVISOR

WITH POWER SUPPLY MONITOR, WATCHDOG

AND BATTERY BACKUP

1

TC70

TC71

Resistor Value Selection

The values of R1 and R2 must be chosen to ensure a

valid low strobe level (VSTL) on RS when the processor I/O

line is low. The use of 10kΩ, ±5% tolerance resistors are

recommended. These values result in a nominal strobe level

of 2.83V on RS (min/max of 2.43V/3.24V, assuming

VDD = 5.0V ±10%). Other resistor values can be used, so

long as the additive tolerances of the power supply and

resistor values result in a strobe that falls within VSTH and

VSTL under all additive tolerance conditions.

External Override Reset Control

A built-in debounce circuit allows a pushbutton switch

(or other electronic reset signal) to be wire-ORed to RS as

an external reset override (Figure 4). The external reset

signal is required to be an active low signal of at least

20msec in duration. Internally, this input is timed to provide

a minimum reset pulse width output of 500msec.

Threshold Detector

The TC71 issues a low-true output on the TDO pin any

time the TDI pin is less than 1.3V and VCC is greater than

VBATT. The voltage to be monitored is connected to the TDI

input through a simple resistor divider. The threshold detec-

tor can be used to generate an early power fail warning if the

unregulated DC input to the +5V regulator is available for

monitoring.

Integrated Battery Backup (TC70)

The CEO line (TC70) drives the CE input of a CMOS

RAM or other device to be battery-backed. CEO follows CEI

as long as VCC is greater than 4.5V nominal. If VCC falls

below 4.5V nominal, CEO is driven to the potential of VCCO

thus write protecting the RAM and preventing accidental

data corruption during power up and power down. The

2 battery switchover circuit compares VCC to the VBATT input

and connects VCCO to whichever is higher. Switchover

(VSW) occurs when VCC is 10mV below VBATT as VCC falls,

and when VCC is 10mV more than VBATT as VCC rises. The

battery switchover comparator has 20mV of hysteresis to

prevent switch chattering if VCC falls very slowly.

Integrated Battery Backup (TC71)

3 The TC71 differs from the TC70 in that it has a Power

Fail (PF) output instead of a gated chip enable (CEI, CEO).

PF must be externally gated with the decode for the CMOS

RAM or other device to be battery-backed. (Many CMOS

RAMs have both CE and CE enables. In this case, the PF

output can be connected directly to the CE input of the RAM).

PF is high as long as VCC is greater than 4.5V nominal.

When VCC falls below 4.5V nominal, PF is driven low.

4 Battery switchover for the TC71 is otherwise identical to that

of the TC70.

Supply Monitor Noise Sensitivity

The TC70/71 is optimized for fast response to negative-

going changes in VDD. Systems with an inordinate amount

of electrical noise on VDD (such as systems using relays),

may require a 0.1µF bypass capacitor to reduce detection

5 sensitivity. This capacitor should be installed as close to the

TC70/71 as possible to keep the capacitor lead length short.

TYPICAL APPLICATIONS

Figure 1 shows a full feature implementation of the

TC70; Figure 2 shows the TC71. Resistors R1 and R2 of

Figure 2 set the trip point voltage for the early power fail

warning circuit using the TC71 threshold detector.

6

WDD

VCCO

+5V

VCC

CEO

VCC

CE

CMOS

RAM

TC70

CEI

VBATT

+3V LI

RS

BATTERY

GND

+5V

R1

10K

ADDRESS

DECODER

R2

13K

RESET

Figure 1. TC70 Typical Application

TELCOM SEMICONDUCTOR, INC.

ADDRESS

I/O

RESET

PROCESSOR

7

8

5-11

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