W40S11-02H 查看數據表（PDF） - SpectraLinear Inc

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W40S11-02H

SDRAM Buffer - 2 DIMM (Mobile)

SpectraLinear Inc 

W40S11-02

How To Use the Serial Data Interface

Electrical Requirements

Figure 1 illustrates electrical characteristics for the serial

interface bus used with the W40S11-02. Devices send data

over the bus with an open drain logic output that can (a) pull

the bus line LOW, or (b) let the bus default to logic 1. The

pull-up resistor on the bus (both clock and data lines) establish

a default logic 1. All bus devices generally have logic inputs to

receive data.

Although the W40S11-02 is a receive-only device (no data

write-back capability), it does transmit an “acknowledge” data

pulse after each byte is received. Thus, the SDATA line can

both transmit and receive data.

The pull-up resistor should be sized to meet the rise and fall

times specified in AC parameters, taking into consideration

total bus line capacitance.

VDD

VDD

SERIAL BUS DATA LINE

SERIAL BUS CLOCK LINE

CLOCK IN

CLOCK OUT

SDCLK

DATA IN

N DATA OUT

~ 2k:

~ 2k:

SDATA

N

CLOCK IN

SCLOCK

DATA IN

DATA OUT

SDATA

N

CHIP SET

(SERIAL BUS MASTER TRANSMITTER)

CLOCK DEVICE

(SERIAL BUS SLAVE RECEIVER)

Figure 1. Serial Interface Bus Electrical Characteristics

Rev 1.0, Dec. 01, 2006

Page 4 of 9

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