GS880Z18BGT-150V 查看數據表（PDF） - Giga Semiconductor

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GS880Z18BGT-150V

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS880Z18/32/36BT-xxxV

AC Test Conditions

Parameter

Conditions

Input high level

VDD – 0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDD/2

Output reference level

VDDQ/2

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Figure 1

Output Load 1

DQ

50Ω

30pF*

VDDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Input Leakage Current

(except mode pins)

FT, ZZ Input Current

Output Leakage Current

Symbol

IIL

IIN

IOL

Test Conditions

VIN = 0 to VDD

VDD ≥ VIN ≥ 0 V

Output Disable, VOUT = 0 to VDD

Min

–1 uA

–100 uA

–1 uA

Max

1 uA

100 uA

1 uA

DC Output Characteristics (1.8 V/2.5 V Version)

Parameter

1.8 V Output High Voltage

2.5 V Output High Voltage

1.8 V Output Low Voltage

2.5 V Output Low Voltage

Symbol

VOH1

VOH2

VOL1

VOL2

Test Conditions

IOH = –4 mA, VDDQ = 1.6 V

IOH = –8 mA, VDDQ = 2.375 V

IOL = 4 mA

IOL = 8 mA

Min

Max

VDDQ – 0.4 V

—

1.7 V

—

—

0.4 V

—

0.4 V

Rev: 1.03 6/2006

16/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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