MU9C8328A-RDC 查看數據表（PDF） - MUSIC Semiconductors
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MU9C8328A-RDC Datasheet PDF : 16 Pages
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MU9C8328A Ethernet Interface
SWITCHING CHARACTERISTICS
No Symbol Parameter (all times in nanoseconds)
Min
Typ
Max Notes
1 tKHKH SYSCLK Period
30
50
2 tKHKL SYSCLK HIGH Pulse Width
0.4 · tKHKH
0.6 · tKHKH
3 tKLKH SYSCLK LOW Pulse Width
0.4 · tKHKH
0.6 · tKHKH
4 tKHCH SYSCLK HIGH to SERCLK HIGH Set-up Time
0
5 tCHKH SERCLK HIGH to SYSCLK HIGH Set-up Time
0
6 tCHCH SERCLK Period
100
7 tCHCL SERCLK HIGH Pulse Width
0.4 · tCHCH
0.6 · tCHCH
8 tCLCH SERCLK LOW Pulse Width
0.4 · tCHCH
0.6 · tCHCH
9 tSLKH Chip or Address Select LOW to SYSCLK HIGH Set-up
10
2
10 tSHKH Chip or Address Select HIGH to SYSCLK HIGH Set-up
10
2
11 tSLSH1 Chip or Address Select LOW Pulse Width - Write Cycle 2 · tKHKH
12 tAVSL Address Bus VALID to Address Select LOW Set-up
5
13 tSLAX Address Select LOW to Address Bus INVALID Hold
10
14 tWVKH Write Enable LOW to SYSCLK HIGH Set-up Time
10
15 tWVWX Write Enable LOW Pulse Width
tKHKH
16 tKHWH SYSCLK HIGH to Write Enable HIGH Hold Time
10
17 tDVKH Data VALID to SYSCLK HIGH Set-up Time
10
18 tKHDX SYSCLK HIGH to Data INVALID Hold Time
10
19 tKHRL SYSCLK HIGH to Ready LOW Delay Time
30
20 tKHRH SYSCLK HIGH to Ready HIGH Delay Time
30
21 tRLRH1 Ready LOW Pulse Width-Write Cycle
tKHKH
22 tTHCH SERDAT HIGH to SERCLK HIGH Set-up Time
10
23 tCHTL SERCLK HIGH to SERDAT LOW Hold Time
10
24 tYLTV NetReady LOW to SERDAT HIGH Set-up Time
10
3
25 tKHJL SYSCLK HIGH to REJECT LOW Delay Time
11 · tKHKH
4
26 tKHDZ1 Chip or Address Select LOW Pulse Width-Read Cycle 2 · tKHKH
27 tKHDV SYSCLK HIGH to Data VALID Delay Time
30
7
28 tKHDZ SYSCLK HIGH to Data HIGH-Z Delay Time
30
8
29 tRLRH2 Ready LOW Pulse Width-CAM Write Cycle
3 · tKHKH
30 tKHEL SYSCLK HIGH to CAM Enable LOW Delay Time
30
31 tKHEH SYSCLK HIGH to CAM Enable HIGH Delay Time
30
32 tKHGV SYSCLK HIGH to CAM Controls VALID Delay Time
30
5
33 tKHGX SYSCLK HIGH to CAM Controls INVALID Delay Time
30
5
34 tEHML CAM Enable HIGH to Match Flag LOW Delay Time
30
6
35 tRHSH Ready HIGH to Chip or Address Select HIGH Set-up
5
36 tSHDZ Chip or Address Select HIGH to Data HIGH-Z Delay
30
37 tKHDX SYSCLK HIGH to Data Bus Active-Read
5
38 tKHDV SYSCLK HIGH to Data Bus VALID Delay Time
50
39 tELQV CAM Enable LOW to DQ Bus VALID-Read
85
6
40 tEHQZ CAM Enable HIGH to DQ Bus HIGH-Z
20
6
Rev. 0.8 Draft
12
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