MU9C8328A-RDC 查看數據表（PDF） - MUSIC Semiconductors
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MU9C8328A-RDC Datasheet PDF : 16 Pages
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MU9C8328A Ethernet Interface
NOTES
1.
-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for input-only lines (Figure 7).
2.
If this timing parameter is violated, the read or write cycle will start one SYSCLK later (assuming /AS or /CS is held).
3.
Before first network data pulse.
4.
From the SYSCLK that strobed the last DA or SA segment into the LANCAM.
5.
LANCAM Controls include /W, /CM, and /EC.
6.
See the LANCAM Handbook for additional information on LANCAM Timing Specs.
7.
With load specified in Figure 5.
8.
With load specified in Figure 6.
9.
Pin A(3)
SYSCLK
SERCLK
Clock Timing
1
2
3
4
5
8
7
6
Processor Interface Write Cycle
SYSCLK
9
/CS
10
11
9
/AS
10
11
12
13
A(2-0)
14
/WE
15
17
16
18
D(15-0)
19
20
READY
21
13
Rev. 0.8 Draft
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