MU9C8328A-RDC 查看數據表（PDF） - MUSIC Semiconductors
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MU9C8328A-RDC Datasheet PDF : 16 Pages
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MU9C8328A Ethernet Interface
PIN DESCRIPTIONS Continued
/WE (Write Enable, Input, TTL)
/WE determines the direction of data flow into or out of the
MU9C8328As processor interface. It also determines the
state of /W to the LANCAM when the processor is
accessing the MU9C8328As internal LANCAM registers.
If /WE is LOW, the data is written into the register selected
by the A(3–0) bus. If /WE is HIGH, then data is read out
of the register selected by the A(3–0) bus.
after both /AS and /CS are LOW. When /WE is HIGH, data
from the selected register is output to the D(15–0) bus on
the second rising edge of SYSLCK after both /AS and /CS
are LOW. For CAM access, the write or read operation is
completed when READY returns HIGH. If /CS is HIGH, or
if data is not being read out of the MU9C8328A, the output
buffers go to HIGH-Z. Internally pulled down with nominal
50K resistor.
A(3–0) (Address Bus, Input, TTL)
A(3–0) select the internal register in the MU9C8328A
accessed by the host processor as shown in Table 1.
A(3–0) are latched by the falling edge of /AS. A(3) is
internally pulled down with a nominal 50K resistor to
maintain compatibility with the MU9C8328.
D(15–0) (Data Bus, I/O, Three-state TTL)
D(15–0) is the processor data bus into and out of the
MU9C8328A, and is demuxed to the internal registers as
selected by the A(2–0) bus. If the register selected is the
Control, Status or Op-Code register, when /WE is LOW,
D(15–0) is loaded on the second rising edge of SYSCLK
READY (Ready, Output, Three-state, TTL)
When writing to the Control, Status, or Op-Code register,
READY goes LOW on the first rising edge of SYSCLK
after both /AS and /CS are LOW and returns HIGH on the
next rising edge of SYSCLK. For a read cycle from those
registers, READY may only show a negative-going spike
at the first rising edge of SYSCLK after both /AS and /CS
are LOW. The data will be valid before the next rising
edge of SYSCLK. When writing to the CAM registers,
READY will go LOW on the first rising edge of SYSCLK
after both /CS and /AS are LOW. READY returns HIGH
three SYSCLK cycles after. When reading from the CAM
registers, READY will return HIGH five SYSCLK cycles later.
81
82
83
/FF
84
/MF
85
/EC
86
/CM
87
/E
88
/W
89
90
GND
91
VCC
92
93
94
/RESET
95
READY
96
/INT
97
/WE
98
/AS
99
/CS
100
MU9C8328A-RDC
100-pin PQFP
(Top View)
Pinout Diagram
3
50
SERCLK
49
SERDAT
48
/REJECT
47
46
45
44
NTE ST OUT
43
42
NTEST_EN (Tie Low)
41
GND
40
VCC
39
38
/NETRDY
37
TEST 1
36
TEST 2
35
TEST 3
34
TEST 4
33
TEST 5
32
D0
31
Rev. 0.8 Draft
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