GS882Z18B-66 查看數據表（PDF） - Unspecified

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GS882Z18B-66

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

Unspecified 

Preliminary.

GS882Z18/36B-11/100/80/66

GS882Z18/36 BGA Pin Description

Pin Location

P4, N4

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, G4, R2, R6, T3, T5

T4

T2, T6

T2, T6

K7, L7, N7, P7, K6, L6, M6, N6, P6

H7, G7, E7, D7, H6, G6, F6, E6, D6

H1, G1, E1, D1, H2, G2, F2, E2, D2

K1, L1, N1, P1, K2, L2, M2, N2, P2

L5, G5, G3, L3

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

L5, G3

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, E1, F2, G1, H2, K1, L2, N2, P1,

G5, L3, T4

K4

M4

H4

E4

B2

B6

F4

B4

T7

R5

R3

R7

J3

J5

Symbol

A0, A1

An

An

NC

An

DQA1–DQPA9

DQB1–DQPB9

DQC1–DQPC9

DQD1–DQPD9

BA, BB, BC, BD

DQA1–DQA9

DQB1–DQB9

BA, BB

NC

CK

CKE

W

E1

E2

E3

G

ADV

ZZ

FT

LBO

PE

DP

QE

D4

ZQ

B1, C1, R1, T1, L4, B7, C7, U6

NC

Type

I

I

I

—

I

I/O

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Inputs (x36 Version)

No Connect (x36 Version)

Address Inputs (x18 Version)

Data Input and Output pins (x36 Version)

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version)

Data Input and Output pins (x18 Version)

Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version)

No Connect (x18 Version)

Clock Input Signal; active high

Clock Input Buffer Enable; active low

Write Enable—Writes all enabled bytes; active low

Chip Enable; active low

Chip Enable; active high

Chip Enable; active low

Output Enable; active low

Burst address counter advance enable; active high

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)

Data Parity Mode Input; 1 = Even, 0 = Odd

Parity Error Out; Open Drain Output

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

No Connect

Rev: 1.15 6/2001

4/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

© 1998, Giga Semiconductor, Inc.

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