WM8734 查看數據表（PDF） - Cirrus Logic
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WM8734 Datasheet PDF : 45 Pages
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WM8734
DACLRC/
ADCLRC
BCLK
Production Data
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section.
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether
Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the
BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input.
BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8734. These are shown in the
figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACDAT/
ADCDAT
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 16 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or
ADCLRC transition.
1/fs
DACLRC/
ADCLRC
LEFT CHANNEL
RIGHT CHANNEL
BCLK
DACDAT/
ADCDAT
1 BCLK
123
MSB
n-2 n-1 n
LSB
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 17 I2S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC
or ADCLRC transition, yet MSB is still transmitted first.
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PD, Rev 4.4, August 2013
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