WM8734 查看數據表（PDF） - Cirrus Logic
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WM8734 Datasheet PDF : 45 Pages
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WM8734
BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Production Data
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tBCY
tBCH
tBCL
tLRSU
50
ns
20
ns
20
ns
10
ns
DACLRC/ADCLRC hold
tLRH
time from BCLK rising edge
10
ns
DACDAT set-up time to
tDS
BCLK rising edge
10
ns
DACDAT hold time from
tDH
BCLK rising edge
10
ns
ADCDAT propagation delay
tDD
from BCLK falling edge
0
10
ns
w
PD, Rev 4.4, August 2013
11
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