datasheetbank_Logo
数据手册搜索引擎和 Datasheet免费下载 PDF

CM8064401831400S 查看數據表(PDF) - Intel

零件编号
产品描述 (功能)
比赛名单
CM8064401831400S Datasheet PDF : 102 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Electrical Specifications—Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families
2.2.3
2.2.4
2.2.5
Figure 1.
DMI2/PCI Express Signals
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or
commands to the PCH. The DMI2 is an extension of the standard PCI Express
Specification. The DMI2/PCI Express Signals consist of DMI2 receive and transmit
input/output signals and a control signal to select DMI2 or PCIe* 2.0 operation for
port 0. Please refer to Table 7 on page 23 for further details.
Intel® QuickPath Interconnect (Intel® QPI)
The processor provides two Intel QPI ports for high speed serial transfer between
other processors. Each port consists of two uni-directional links (for transmit and
receive). A differential signaling scheme is utilized, which consists of opposite-polarity
(DP, DN) signal pairs.
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external system management logic and
thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides
an interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics.
The PECI interface operates at a nominal voltage set by VCCPECI. The set of DC
electrical specifications shown in PECI DC Specifications on page 38 is used with
devices normally operating from a VCCPECI interface supply.
Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Please refer to the following image and PECI DC
Specifications on page 38.
Input Device Hysteresis
-VCCPECI
-Maximum VP
-Minimum VP
-Maximum VN
-Minimum VN
-PECI Ground
PECI High Range
PECI Low Range
Minimum
Hysteresis
Valid Input
Signal Range
June 2015
Order No.: 330783-002
Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical
Datasheet
15

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]