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Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical

Intel 

Intel® Xeon® Processor E5-1600 and E5-2600 v3 Product Families—Electrical Specifications

2.2.6

2.2.7

2.2.8

System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN)

The processor Core, processor Uncore, Intel® QuickPath Interconnect link, PCI

Express* and DDR4 memory interface frequencies) are generated from

BCLK{0/1}_DP and BCLK{0/1}_DN signals. There is no direct link between core

frequency and Intel QuickPath Interconnect link frequency (e.g., no core frequency to

Intel QuickPath Interconnect multiplier). The processor maximum core frequency,

Intel QuickPath Interconnect link frequency and DDR memory frequency are set

during manufacturing. It is possible to override the processor core frequency setting

using software (see the Intel® 64 and IA-32 Architectures Software Developer's

Manuals). This permits operation at lower core frequencies than the factory set

maximum core frequency.

The processor core frequency is configured during reset by using values stored within

the device during manufacturing. The stored value sets the lowest core multiplier at

which the particular processor can operate. If higher speeds are desired, the

appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits

[15:0]. For details of operation at core frequencies lower than the maximum rated

processor speed, refer to the Intel® 64 and IA-32 Architectures Software Developer's

Manuals .

Clock multiplying within the processor is provided by the internal phase locked loop

(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with

exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,

BCLK{0/1}_DN inputs are provided in Processor Asynchronous Sideband DC

Specifications on page 42. These specifications must be met while also meeting the

associated signal quality specifications outlined in Signal Quality on page 45.

JTAG and Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the JTAG and Test Access

Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by

any other components within the system. Please refer to the Intel®Xeon® Processor

E5-1600 and E5-2600 v3 Product Family Boundary Scan Description Language (BSDL)

file more details. A translation buffer should be used to connect to the rest of the

chain unless one of the other components is capable of accepting an input of the

appropriate voltage. Two copies of each signal may be required with each driving a

different voltage level.

Processor Sideband Signals

The Intel® Xeon® processor E5-1600 and E5-2600 v3 product families includes

asynchronous sideband signals that provide asynchronous input, output or I/O signals

between the processor and the platform or Platform Controller Hub. Details can be

found in Table 7 on page 23.

All Processor Asynchronous Sideband input signals are required to be asserted/de-

asserted for a defined number of BCLKs in order for the processor to recognize the

proper signal state, these are outlined in Processor Asynchronous Sideband DC

Specifications on page 42 (DC specifications). Refer to Signal Quality on page 45

for applicable signal integrity specifications.

Intel® Xeon® Processor E5-1600, E5-2600, and E5-4600 v3 Product Families, Volume 1 of 2, Electrical

Datasheet

16

June 2015

Order No.: 330783-002

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