HEF4081B-Q100 查看數據表（PDF） - NXP Semiconductors.

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HEF4081B-Q100

Quad 2-input AND gate

NXP Semiconductors. 

Nexperia

11. Waveforms

HEF4081B-Q100

Quad 2-input AND gate

VI

nA, nB input

10 %

0V

tr

90 %

VM

tPLH

VOH

nY output

VOL

10 %

90 %

VM

tTLH

tf

tPHL

tTHL

001aai140

Fig 4.

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Input to output propagation delay and output transition times

Table 9. Measurement points

Supply voltage

VDD

5 V to 15 V

Input

VM

0.5VDD

Output

VM

0.5VDD

VDD

VI

G

VO

DUT

RT

CL

001aag182

Fig 5.

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL = load capacitance including jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Test circuit

Table 10. Test data

Supply voltage

VDD

5 V to 15 V

Input

VI

VSS or VDD

tr, tf

 20 ns

Load

CL

50 pF

HEF4081B_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 13 November 2013

© Nexperia B.V. 2017. All rights reserved

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