TC7MP245FTG 查看數據表（PDF） - Toshiba

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TC7MP245FTG

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

Pin Assighment (top view)

FK (VSSOP20-P-0030-0.50)

DIR 1

A1 2

A2 3

A3 4

A4 5

A5 6

A6 7

A7 8

A8 9

GND 10

20 VCC

19 OE

18 B1

17 B2

16 B3

15 B4

14 B5

13 B6

12 B7

11 B8

TC7MP245FK/FTG

FTG (VQON20-P-0404-0.50)

A1 DIR VCC OE B1

20 19 18 17 16

A2 1

A3 2

A4 3

A5 4

A6 5

15 B2

14 B3

13 B4

12 B5

11 B6

6 7 8 9 10

A7 A8 GND B8 B7

Truth Table

Marking

Input

DIR

OE

L

L

H

L

X

H

Bus state

B→A(B=A)

A→B(A=B)

Z

Bus hold circuit

(B bus)

OFF

OFF

ON*

X: Don’t care

Z: High impedance

*: Logic state just before becoming disable is maintained.

Note: When a bus input is in "H" state ,and an output is switched to

"enable" to "disable", Glitch such as "L" state during about

1 to 3ns occurs in an output. It is not generated when a bus

input is in "L" state.

FTG (VQON20-P-0404-0.50)

P 0 0A

****

1 pin

Product Name

Lot trace code

System Diagram

OE

DIR

A1

1/8

2

B1

2007-10-19

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