F12N10L 查看數據表（PDF） - Fairchild Semiconductor
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F12N10L Datasheet PDF : 6 Pages
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RFP12N10L
Typical Performance Curves Unless Otherwise Specified (Continued)
1.3
VDS = VGS
1.2 ID = 250µA
1.1
1.0
0.9
0.8
0.7
0.6
0.5
-50
0
50
100
150
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
800
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
600
COSS ≈ CDS + CGD
CISS
400
200
COSS
CRSS
0
0
10
20
30
40
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 8. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100 BVDSS
10
RL = 8.33Ω
IG (REF) = 0.56mA
8
75
VGS = 5V
GATE
VDD
=
BVDSS
SOURCE
VOLTAGE
VDD
=
BVDSS
6
50
4
25
0.75BVDSS
0.50BVDSS
0.25BVDSS
DRAIN SOURCE
VOLTAGE
0
20 IG (REF)
IG (ACT)
t, TIME (µs)
2
0
80 IG (REF)
IG (ACT)
NOTE: Refer to Fairchild Applications Notes AN7254 and AN7260
FIGURE 9. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
RL
+
RG
VDD
-
DUT
VGS
FIGURE 10. SWITCHING TIME TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 11. RESISTIVE SWITCHING WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFP12N10L Rev. B
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