UPD78C18GQ-XXX-36 查看數據表（PDF） - NEC => Renesas Technology
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UPD78C18GQ-XXX-36 Datasheet PDF : 110 Pages
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1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTION (1/2)
µPD78C17,78C18
Pin Name
PA7 to PA0
(Port A)
PB7 to PB0
(Port B)
PC0/TXD
PC1/RxD
PC2/SCK
PC3/INT2/TI
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
PD7 to PD0/
AD7 to AD0
PF7 to PF0/
AB15 to AB8
WR
(Write Strobe)
RD
(Read Strobe)
ALE
(Address Latch
Enable)
I/O
Function
Input-output 8-bit input-output port, which can specify input/output (Port A) bit-wise.
Input-output 8-bit input-output port, which can specify input/output (Port B) bit-wise.
Input-output/
Output
Input-output/
Input
Port C
8-bit input-output port,
which can specify input/output bit-wise.
Input-output/
Input-output
Transmit Data
Output pin for serial data.
Receive Data
Input pin for serial data.
Serial Clock
Input-output pin for serial clock.
It becomes output pin for the internal clock
use, and input pin for the external.
Input-output/
Input/Input
Interrupt Request/Timer Input
Maskable interrupt input pin of the
edge trigger (falling edge), or an
external clock input pin for a timer.
Also, it can be used as a zero-cross
detection pin for AC input.
Input-output/
Output
Timer Output
Square wave defining one cycle of
internal clock or timer counter time as
half cycle is output.
Input-output/
Input
Counter Input
External pulse input pin to timer/event
counter.
Input-output/
Output
Counter Output 0, 1
Programmable square wave output by
timer/event counter.
Input-output/ Port D
Input-output 8-bit input-output port, which can specify
input/output in byte units (µPD78C18).
Address/Data Bus
When external memory is used, it
becomes multiplexed address/data bus.
Input-output/ Port F
Output
8-bit input-output port, which can specify
input/output bit-wise.
Address Bus
When external memory is used, it
becomes address bus.
Output
Strobe signal which is output for write operation of external memory. It becomes high
in any cycle other than the data write machine cycle of external memory. When RESET
signal is either low or in the hardware STOP mode, this signal becomes output high-
impedance.
Output
Strobe signal which is output for read operation of external memory. It becomes high in
any cycle other than the read machine cycle of external memory. When RESET signal is
either low or in the hardware STOP mode, this signal becomes output high-impedance.
Output
Strobe signal to latch externally the lower address information which is output to PD7 to
PD0 pins to access external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes output high-impedance.
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