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UPD78C18GQ-XXX-36 查看數據表(PDF) - NEC => Renesas Technology

零件编号
产品描述 (功能)
比赛名单
UPD78C18GQ-XXX-36
NEC
NEC => Renesas Technology NEC
UPD78C18GQ-XXX-36 Datasheet PDF : 110 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
1.1 LIST OF PIN FUNCTION (2/2)
µPD78C17,78C18
Pin Name
MODE0
MODE1
(Mode)
NMI
(Non-Maskable
Interrupt)
INT1
(Interrupt
Request)
AN7 to AN0
(Analog Input)
VAREF
(Reference
Voltage)
AVDD
(Analog VDD)
AVSS
(Analog VSS)
X1, X2
(Crystal)
RESET
(Reset)
STOP
(Stop)
VDD
VSS
I/O
Function
Input-output
The µPD78C18 sets MODE0 pin to “0” (low level), and MODE1 pin to “1” (high level).Note
The µPD78C17 allows you to set MODE0, MODE1 pins to select 4 K, 16 K, or 63 Kbytes for
the size of the memory which is installed externally.
Input
MODE0 MODE1 External Memory
0
0
4 Kbytes
1
0
16 Kbytes
1
1
63 Kbytes
Also, when each of MODE0 and MODE1 pins is set to “1”Note, it is synchronized to ALE to
output a control signal.
Non-maskable interrupt input pin of the edge trigger (falling edge)
Input
Input
Input
Input
Input
A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a
zero-cross detection pin for AC input.
8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection
(falling edge) input.
A common pin serving both as a reference voltage input pin for A/D converter and as a
control pin for A/D converter operation.
Power supply pin for A/D converter.
GND pin for A/D converter.
Crystal connection pins for system clock oscillation. X1 should be input when a clock is
supplied from outside. Inverted clock of X1 should be input to X2.
Low-level active system reset input.
Control signal input pin in hardware STOP mode. The oscillation stops when the low-
level is input.
Positive power supply pin.
GND pin.
Note
Connect a pull-up resistor. Resistance R should be 4 [k] R 0.4tCYC [k] (tCYC is in nanoseconds).
Remark The µPD78C18 can incorporate (mask option) pull-up resistors on to ports A, B, and C.
8

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