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SPT5140 查看數據表(PDF) - Cadeka Microcircuits LLC.

零件编号
产品描述 (功能)
比赛名单
SPT5140
CADEKA
Cadeka Microcircuits LLC. CADEKA
SPT5140 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Figure 5 – CONVert, CONVert Switching Levels
VIDF
0.0 V
VICM MIN
VICM MAX
–1.3 V
CONV
CONV
CONVERT CLOCK
For best performance, the clock should be ECL driven,
differentially, by utilizing CONV and CONV (figure 5). By
driving the clock this way, clock noise and power supply/
output intermodulation will be minimized. The rising edge
of the clock synchronizes the data and control inputs to
the SPT5140. Since the actual switching threshold of
CONV is determined by CONV , the clock can be driven
single-ended by connecting a bias voltage to CONV. The
switching threshold of CONV is set by this bias voltage.
ANALOG OUTPUTS
The SPT5140 has two analog outputs that are high im-
pedance, complementary current sinks. The outputs vary
in proportion to the input data, controls and reference cur-
rent values so that the full-scale output can be changed
by setting ISet as mentioned earlier.
In video applications, the outputs can drive a doubly ter-
minated 50 or 75 ohm load to standard video levels. In
the standard configuration of figure 6, the output voltage
is the product of the output current and load impedance
and is between 0 and –1.07 V. The Out– output (figure 4)
will provide a video output waveform with the Sync pulse
bottom at the –1.07 V level. The Out+ is inverted with
Sync up.
Figure 6A – Standard Load
Video Monitor
OUT –
75 COAX
RS
75
RL
75
SPT5140
OUT +
RS
75
75 COAX
Inverse
Video
RL
75
Figure 6B – Test Load
OUT +
OUT –
CL
<5 pF
RL
37.5
Video Out
0 to –1 Volt
Figure 7 – Burn-In Circuit
–5.9 V
(Max 200 mA)
6.5
6.5
24-Pin DIP
All Resistors Are 5% 1/4 W cc
Clock = –0.9 to –1.7 V, 100 kHz
–1.2 V
(Max 1.5 mA)
1 k
VEE
Ref In
Out–
(Max 50 mA)
(Max 50 mA)
Out+
100
100
–1.3 V
(Max 60 µA)
1 k
Clock
(Max 60 µA)
1 k
CONV
CONV
1 k
ISet
(Max 1.5 mA)
VCC
SPT5140
8
3/28/00

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