datasheetbank_Logo
数据手册搜索引擎和 Datasheet免费下载 PDF

CY7C1329_04 查看數據表(PDF) - Cypress Semiconductor

零件编号
产品描述 (功能)
比赛名单
CY7C1329_04
Cypress
Cypress Semiconductor Cypress
CY7C1329_04 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY7C1329
Interleaved Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
00
11
10
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
A[1:0]
00
01
10
11
Second
Address
A[1:0]
01
10
11
00
Third
Address
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
Description
Snooze mode standby cur-
rent
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD 0.2V
ZZ > VDD 0.2V
ZZ < 0.2V
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Min.
2tCYC
Max.
3
2tCYC
Unit
mA
ns
ns
Cycle Descriptions [1,2,3]
Next Cycle Add. Used ZZ
Unselected
None
L
CE3 CE2 CE1 ADSP ADSC ADV
X
X
1
X
0
X
Unselected
None
L
1
X
0
0
X
X
Unselected
None
L
X
0
0
0
X
X
Unselected
None
L
1
X
0
1
0
X
Unselected
None
L
X
0
0
1
0
X
Begin Read
External
L
0
1
0
0
X
X
Begin Read
External
L
0
1
0
1
0
X
Continue Read Next
L
X
X
X
1
1
0
Continue Read Next
L
X
X
X
1
1
0
Continue Read Next
L
X
X
1
X
1
0
Continue Read Next
L
X
X
1
X
1
0
Suspend Read Current
L
X
X
X
1
1
1
Suspend Read Current
L
X
X
X
1
1
1
Suspend Read Current
L
X
X
1
X
1
1
Suspend Read Current
L
X
X
1
X
1
1
Begin Write
Current
L
X
X
X
1
1
1
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
OE
DQ Write
X Hi-Z X
X Hi-Z X
X Hi-Z X
X Hi-Z X
X Hi-Z X
X Hi-Z X
X Hi-Z Read
1 Hi-Z Read
0 DQ Read
1 Hi-Z Read
0 DQ Read
1 Hi-Z Read
0 DQ Read
1 Hi-Z Read
0 DQ Read
X Hi-Z Write
Document #: 38-05279 Rev. *B
Page 5 of 15

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]