AV9148F-02 查看數據表（PDF） - Integrated Circuit Systems

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AV9148F-02

Pentium/Pro™ System Clock Chip

Integrated Circuit Systems 

ICS9148-02

Select Functions

Functionality

Tristate

Testmode

CPU

HI - Z

TCLK/21

PCI,

PCI_F

HI - Z

TCLK/41

SDRAM

HI - Z

TCLK/21

REF

HI - Z

TCLK1

IOAPIC

HI - Z

TCLK1

24 MHz

Selection

HI - Z

TCLK/41

48 MHz

Selection

HI - Z

TCLK/21

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

Byte 1: CPU, 24/48 MHz Clock Register

BIT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIN#

23

22

-

-

38

39

41

42

PWD

1

1

1

1

1

1

1

1

DESCRIPTION

48/24 MHz (Act/Inact)

48/24 MHz (Act/Inact)

Reserved

Reserved

CPUCLK3 (Act/Inact)

CPUCLK2 (Act/Inact)

CPUCLK1 (Act/Inact)

CPUCLK0 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 3: SDRAM Clock Register

BIT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIN#

26

27

29

30

32

33

35

36

PWD

1

1

1

1

1

1

1

1

DESCRIPTION

SDRAM7 (Act/Inact)

SDRAM6 (Act/Inact)

SDRAM5 (Act/Inact)

SDRAM4 (Act/Inact)

SDRAM3 (Act/Inact)

SDRAM2 (Act/Inact)

SDRAM1(Act/Inact)

SDRAM0 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

Byte 2: PCICLK Clock Register

BIT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIN#

-

8

16

14

13

12

11

9

PWD

1

1

1

1

1

1

1

1

DESCRIPTION

Reserved

PCICLK_F (Act/Inact)

PCICLK5 (Act/Inact)

PCICLK4 (Act/Inact)

PCICLK3 (Act/Inact)

PCICLK2 (Act/Inact)

PCICLK1 (Act/Inact)

PCICLK0 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 4: SDRAM Clock Register

BIT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIN#

-

-

-

-

-

-

-

-

PWD

DESCRIPTION

1 Reserved

1 Reserved

1 Reserved

1 Reserved

1 Reserved

1 Reserved

1 Reserved

1 Reserved

Notes: 1 = Enabled; 0 = Disabled, outputs held low

7

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