CL7128E 查看數據表（PDF） - Clear Logic
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CL7128E Datasheet PDF : 16 Pages
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CL7128E and CL7128S Laser Processed Logic Devices
AC Electrical Specifications cont.
External Timing Parameters
Speed: -10P
Symbol
Parameter
Conditions Min Max
tPD1 Input to non-registered output
CL = 35 pF
10.0
tPD2 I/O input to non-registered output
CL = 35 pF
10.0
tSU Global clock setup time
7.0
tH
Global clock hold time
0.0
tFSU Global clock setup time of fast input
3.0
tFH Global clock hold time of fast input
0.5
tCO1 Global clock to output delay
CL = 35 pF
5.0
tCH Global clock high time
4.0
tCL Global clock low time
4.0
tASU Array clock setup time
2.0
tAH Array clock hold time
3.0
tACO1 Array clock to output delay
CL = 35 pF
10.0
tACH Array clock high time
4.0
tACL Array clock low time
4.0
tODH Output data hold time after clock
CL = 35 pF
1.0
tCNT Minimum global clock period
10.0
fCNT Max. internal global clock frequency
100.0
tACNT Minimum array clock period
10.0
fACNT Max. internal array clock frequency
100.0
Speed: -10
Min Max
10.0
10.0
7.0
0.0
3.0
0.5
5.0
4.0
4.0
2.0
5.0
10.0
4.0
4.0
1.0
10.0
100.0
10.0
100.0
Speed: -12
Min Max Unit
12.0 ns
12.0 ns
10.0
ns
0.0
ns
3.0
ns
0.0
ns
6.0 ns
4.0
ns
4.0
ns
4.0
ns
4.0
ns
12.0 ns
5.0
ns
5.0
ns
1.0
ns
11.0 ns
90.9
MHz
11.0 ns
90.9
MHz
7K tbl 06B2
Page 8
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