5P49V5901ADDDNLGI8 查看數據表（PDF） - Integrated Device Technology
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5P49V5901ADDDNLGI8 Datasheet PDF : 35 Pages
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IDT5P49V5901
PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Number
22
23
Name
VDDD
VDDO0
Type
Power
Power
24
OUT0_SEL_I2CB
Input/
Output
Internal
Pull-down
ePAD
GND
GND
Description
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDD
should have the same voltage applied.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and
9 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull
down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and
9 will act as the SDA and SCL pins of an I2C interface. After power up, the pin
acts as a LVCMOS reference output.
Connect to ground pad.
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
IDT5P49V5901 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread
energy across a broader range of frequencies, lowering
system EMI. The IDT5P49V5901 implements spread
spectrum using the Fractional-N output divide, to achieve
controllable modulation rate and spreading magnitude. The
Spread spectrum can be applied to any output clock, any
clock frequency, and any spread amount from ±0.25% to
±2.5% center spread and -0.5% to -5% down spread.
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Frequency–Fref
(MHz)
5
350
Loop
Bandwidth
Min (kHz)
40
300
Loop
Bandwidth
Max (kHz)
126
1000
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be
stored in OTP. These can be factory programmed or user
programmed.
SEL1
0
0
1
1
SEL0
0
1
0
1
CONFIG
0
1
2
3
SEL0,1 pins must be changed within ~100ns of each other
and then the device left alone for 1ms. Refer to
OUT0_SEL_I2CB pin description.
Table 4: Input Clock Select
Input clock select. Selects the active input reference source
in manual switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as
shown in Table 4.
PRIMSRC
0
0
1
1
CLKSEL
0
1
0
1
Source
XIN/REF
CLKIN, CLKINB
CLKIN, CLKINB
XIN/REF
PRIMSRC is bit 1 of Register 0x13.
IDT® PROGRAMMABLE CLOCK GENERATOR
4
IDT5P49V5901
REV A 031014
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