5P49V5901ADDDNLGI8 查看數據表（PDF） - Integrated Device Technology

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5P49V5901ADDDNLGI8

PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

Table 6: I2C Bus DC Characteristics

Symbol

Parameter

Conditions

VIH

VIL

VHYS

IIN

VOL

Input HIGH Level

Input LOW Level

Hysteresis of Inputs

Input Leakage Current

Output LOW Voltage

IOL = 3 mA

Table 7: I2C Bus AC Characteristics

Min

Typ

Max Unit

0.7xVDDD

0.05xVDDD

V

0.3xVDDD V

V

±1.0

µA

0.4

V

Symbol

Parameter

Min

Typ

Max Unit

FSCLK

tBUF

tSU:START

tHD:START

tSU:DATA

tHD:DATA

tOVD

CB

tR

tF

tHIGH

tLOW

tSU:STOP

Serial Clock Frequency (SCL)

Bus free time between STOP and START

Setup Time, START

Hold Time, START

Setup Time, data input (SDA)

Hold Time, data input (SDA) 1

Output data valid from clock

Capacitive Load for Each Bus Line

Rise Time, data and clock (SDA, SCL)

Fall Time, data and clock (SDA, SCL)

HIGH Time, clock (SCL)

LOW Time, clock (SCL)

Setup Time, STOP

0

1.3

0.6

0.6

100

0

20 + 0.1xCB

20 + 0.1xCB

0.6

1.3

0.6

400

kHz

µs

µs

µs

ns

µs

0.9

µs

400

pF

300

ns

300

ns

µs

µs

µs

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

IDT® PROGRAMMABLE CLOCK GENERATOR

9

IDT5P49V5901

REV A 031014

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