AS5040(2004) 查看數據表（PDF） - austriamicrosystems AG
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AS5040 Datasheet PDF : 20 Pages
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AS5040 10-BIT PROGRAMMABLE MAGNETIC ROTARY ENCODER
Incremental Mode Programming
Three different incremental output modes are available.
Mode: Md1=0 / Md0=1 sets the AS5040 in quadrature
mode.
Mode: Md1=1 / Md0=0 sets the AS5040 in single channel
mode with direction indicator (see Table 1 )
In both modes the incremental resolution can be reduced
from 10 bit down to 9, 8 or 7 bit using the divider OTP
bits Div1 and Div0. Md0 or Md1 must additionally set for
that purpose.
Mode: Md1=1 / Md0=1 sets the AS5040 in brushless DC
motor commutation mode with an additional LSB
incremental signal at pin 12 (PWM_LSB).
To allow programming of all bits, the default facatory
setting is all bits = 0. This mode is equal to mode 1:0
(quadrature AB, 1LSB index width, 256ppr).
The absolute angular output value, by default, increases
if the magnet, placed either above or below the chip,
turns clockwise (top view). Setting the CCW-bit (see
Figure 11) allows for reversing the indicated direction,
e.g. when the magnet is placed underneath the IC.(CCW
= 0 - angular value increases clockwise; CCW = 1 –
angular value increases counter clockwise).
By default, the zero / index position pulse is one LSB
wide. However, it can be increased to a three LSB wide
pulse by setting the Index-bit of the OTP Register. This
is especially useful for high speed operation, where the
index signal output may be just a small glitch otherwise.
Especially for brush-less DC motor-control, further
programmable options are available (Commutation-
Modes), are available. Md1 = Md0 = 1 changes the
incremental output pins 3,4 and 6 to a 3-phase
commutation signal. Div1 defines the number of pulses
per revolution for either a single-pole (Div1=0) or two-
pole pair (Div1=1) motor operation. In addition, the LSB
is available at pin 12 (the LSB signal replaces the PWM-
signal), which allows for high rotational speed
measurement of up to 10,000 rpm.
OTP-Mode-Register-Bit
PIN #
Pulses per Incremental
Revolution Resolution
Mode
Md1
Md0
Div1
Div0
Inde
x
3
4
6
12
ppr
bit
Default (Mode0.0)
0
0
0*
0*
0*
1LSB
quadAB-Mode1.0
0
1
0
0
0
1LSB
2x256
10
quadAB-Mode1.1
0
1
0
0
1
3LSBs
quadAB-Mode1.2
0
1
0
1
0
1LSB
quadAB-Mode1.3
0
1
0
1
1
A
B
3LSBs
PWM
10bit
2x128
9
quadAB-Mode1.4
0
1
1
0
0
quadAB-Mode1.5
0
1
1
0
1
1LSB
3LSBs
2x64
8
quadAB-Mode1.6
0
1
1
1
0
quadAB-Mode1.7
0
1
1
1
1
1LSB
3LSBs
2x32
7
LSB/Dir-Mode2.0
1
0
0
0
0
LSB/Dir-Mode2.1
1
0
0
0
1
1LSB
3LSBs
512
10
LSB/Dir -Mode2.2
1
0
0
1
0
1LSB
256
9
LSB/Dir -Mode2.3
1
0
0
1
1
LSB
LSB/Dir -Mode2.4
1
0
1
0
0
Dir
3LSBs
1LSB
PWM
10bit
128
8
LSB/Dir -Mode2.5
1
0
1
0
1
3LSBs
LSB/Dir -Mode2.6
1
0
1
1
0
LSB/Dir -Mode2.7
1
0
1
1
1
1LSB
3LSBs
64
7
Commutation-Mode3.0 1
1
0
0
0
10
U(0º)
V(120º) W(240º) LSB
3x1
Commutation-Mode3.1 1
1
0
1
0
9
Commutation-Mode3.2 1
Commutation-Mode3.3 1
1
1
1
1
0
1
0
0
U’
(0º, 180º)
V’
W’
(60º,240º) (120º,300º)
LSB
2x3
10
9
Table 7: One Time Programmable (OTP) register options
.*Note: Div1,Div0 and Index cannot be programmed in Mode 0:0
Revision 1.1
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