ADSP-2171 查看數據表（PDF） - Analog Devices
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ADSP-2171 Datasheet PDF : 52 Pages
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ADSP-2171/ADSP-2172/ADSP-2173
Pin Description
The ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I. ADSP-217x Pin List
Pin
Group
Name
#
of Input/
Pins Output Function
Address
Data
14 O
24 I/O
RESET
IRQ2
BR
BG
BGH
PMS
DMS
BMS
RD
WR
MMAP
CLKIN,
XTAL
1I
1I
1I
1O
1O
1O
1O
1O
1O
1O
1I
2I
CLKOUT 1 O
HSEL
1I
HACK
1O
HSIZE
1
BMODE 1 I
HMD0
1I
HMD1
1I
HRD/HRW 1 I
HWR/HDS 1 I
HD15–0/
HAD15-0
HA2/ALE
16 I/O
1I
HA1–0/
Unused
2I
SPORT0 5 I/O
Address output for program,
data and boot memory spaces
Data I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2
External bus request input
External bus grant output
External bus grant hang output
External program memory select
External data memory select
Boot memory select
External memory read enable
External memory write enable
Memory map select
External clock or quartz crystal
input
Processor clock output
HIP select input
HIP acknowledge output
8/16 bit host select input
0 = 16-bit; 1 = 8-bit
Boot mode select input
0 = EPROM/data bus; 1 = HIP
Bus strobe select input
0 = RD, WR; 1 = RW, DS
HIP address/data mode select
input 0 = separate; 1 =
multiplexed
HIP read strobe/read/write
select input
HIP write strobe/host data
strobe select input
HIP data/data and address
Host address 2/Address latch
enable input
Host addresses 1 and 0 inputs
Serial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT1 5 I/O
or
IRQ1 (TFS1) 1 I
IRQ0 (RFS1) 1 I
SCLK1
1O
FO (DT1) 1 O
FI (DR1) 1 I
FL2–0
3O
VDD
6
GND
11
PWD
1I
PWDACK 1 O
Serial port 1 I/O pins
External interrupt request #1
External interrupt request #0
Programmable clock output
Flag Output pin
Flag Input pin
General purpose flag output
pins
Power supply pins
Ground pins
Powerdown pin
Powerdown acknowledge pin
Host Interface Port
The ADSP-217x host interface port is a parallel I/O port that al-
lows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped periph-
eral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow commu-
nication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
• HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
• BMODE (when MMAP = 0) determines whether the ADSP-
217x boots from the host processor (through the HIP) or ex-
ternal EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
Tying these pins to appropriate values configures the ADSP-
217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional informa-
tion refer to the ADSP-2100 Family User’s Manual.
HIP Operation
The HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed us-
ing either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
–4–
REV. A
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