ADSP-2171 查看數據表（PDF） - Analog Devices

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ADSP-2171

DSP Microcomputer

Analog Devices 

ADSP-2171/ADSP-2172/ADSP-2173

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

The ADSP-217x provides up to three external interrupt input

pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-

cated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and

the flags. The ADSP-217x also supports internal interrupts from

the timer, the host interface port, the two serial ports, software,

and the powerdown control circuit. The interrupt levels are in-

ternally prioritized and individually maskable (except power-

down and reset). The input pins can be programmed to be

either level- or edge-sensitive. The priorities and vector ad-

dresses of all interrupts are shown in Table II, and the interrupt

registers are shown in Figure 2.

Interrupts can be masked or unmasked with the IMASK regis-

ter. Individual interrupt requests are logically ANDed with the

bits in IMASK; the highest priority unmasked interrupt is then

selected.The powerdown interrupt is nonmaskable.

The ADSP-217x masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. This does not affect autobuffering.

The interrupt control register, ICNTL, allows the external in-

terrupts to be either edge- or level-sensitive. Interrupt routines

can either be nested with higher priority interrupts taking prece-

dence or processed sequentially.

The IFC register is a write-only register used to force and clear

interrupts generated from software.

Table II. Interrupt Priority & Interrupt Vector Addresses

Source of Interrupt

Interrupt Vector

Address (Hex)

Reset (or Power-Up with PUCR = 1)

Powerdown (Nonmaskable)

IRQ2

HIP Write

HIP Read

SPORT0 Transmit

SPORT0 Receive

Software Interrupt 1

Software Interrupt 0

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

0000 (Highest Priority)

002C

0004

0008

000C

0010

0014

0018

001C

0020

0024

0028 (Lowest Priority)

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling.

The stacks are twelve levels deep to allow interrupt nesting.

The following instructions allow global enable or disable servic-

ing of the interrupts (including powerdown), regardless of the

state of IMASK. Disabling the interrupts does not affect

autobuffering.

ENA INTS;

DIS INTS;

When you reset the processor, the interrupt servicing is enabled.

ICNTL

43210

0

IMASK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 = enable, 0 = disable

IRQ0 Sensitivity

IRQ1 Sensitivity

IRQ2 Sensitivity

1 = edge

0 = level

Interrupt Nesting

1 = enable, 0 = disable

IRQ2

HIP Write

HIP Read

SPORT0 Transmit

SPORT0 Receive

IFC

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 000 0 0 0 0 0 0 0 0 0 0

Timer

IRQ0 or SPORT1 Receive

IRQ1 or SPORT1 Transmit

Software 0

Software 1

INTERRUPT FORCE

IRQ2

SPORT0 Transmit

SPORT0 Receive

Software 1

Software 0

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

INTERRUPT CLEAR

Timer

SPORT1 Receive or IRQ0

SPORT1 Transmit or IRQ1

Software 0

Software 1

SPORT0 Receive

SPORT0 Transmit

IRQ2

Figure 2. Interrupt Registers

REV. A

–5–

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