M62364FP
Timing Chart (Model)
RESET
DI
MSB
LSB
D11 D10 D9
............
D0
CLK
............
LD
Vo
Note: Input data is carried out LD signal low besides CLK signal positive edge. CLK, LD is keep generally
high level.
REJ03D0875-0300 Rev.3.00 Mar 25, 2008
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