ADP3419 查看數據表（PDF） - Analog Devices
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ADP3419 Datasheet PDF : 16 Pages
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Dual Bootstrapped, High Voltage MOSFET
Driver with Output Disable
ADP3419
FEATURES
All-in-one synchronous buck driver
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable function
Crowbar control
Synchronous override control
Undervoltage lockout
APPLICATIONS
Mobile computing CPU core power converters
Multiphase desk-note CPU supplies
Single-supply synchronous buck converters
Nonsynchronous-to-synchronous drive conversion
GENERAL DESCRIPTION
The ADP3419 is a dual MOSFET driver optimized for driving
two N-channel switching MOSFETs in nonisolated synchro-
nous buck power converters used to power CPUs in portable
computers. The driver impedances have been chosen to provide
optimum performance in multiphase regulators at up to 25 A
per phase. The high-side driver can be bootstrapped relative to
the switch node of the buck converter and is designed to
accommodate the high voltage slew rate associated with floating
high-side gate drivers.
The ADP3419 includes an anticross-conduction protection
circuit, undervoltage lockout to hold the switches off until the
driver has sufficient voltage for proper operation, a crowbar
input that turns on the low-side MOSFET independently of the
input signal state, and a low-side MOSFET disable pin to
provide higher efficiency at light loads. The SD pin shuts off
both the high-side and the low-side MOSFETs to prevent rapid
output capacitor discharge during system shutdown.
The ADP3419 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 10-lead
MSOP package.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
VCC
5
BST
10
IN 1
SD 2
DRVLSD 3
CROWBAR 4
UVLO,
OVERLAP
PROTECTION,
SHUTDOWN
AND
CROWBAR
CIRCUITS
ADP3419
7
GND
Figure 1.
9 DRVH
8 SW
6 DRVL
GENERAL APPLICATION CIRCUIT
5V
VDC
FROM CONTROLLER
PWM OUTPUT
FROM SYSTEM
ENABLE CONTROL
FROM
CONTROLLER
FROM CONTROLLER
CLAMP OUTPUT
5
VCC
1 IN
BST 10
ADP3419
2 SD
DRVH 9
3 DRVLSD
SW 8
4 CROWBAR DRVL 6
GND
7
Figure 2.
VOUT
Rev. A
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