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ADP3419 查看數據表(PDF) - Analog Devices

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ADP3419 Datasheet PDF : 16 Pages
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ADP3419
SPECIFICATIONS
VCC = SD = 5 V, BST = 4 V to 26 V, TA = 0°C to 100°C, unless otherwise noted.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Table 1.
Parameter
LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)
Input Voltage High
Input Voltage Low
Input Current
DRVLSD Propagation Delay Time
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
Propagation Delay Times1
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
Propagation Delay Times1, 2
SW Transition Timeout2
Zero-Crossing Threshold
SUPPLY
Supply Voltage Range
Supply Current
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis3
Symbol
VIH
VIL
IIN
tpdlDRVLSD,
tpdhDRVLSD
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
tSWTO
VZC
VCC
ISYS(NM)
ISYS(SD)
Conditions
Inputs = 0 V or 5 V
CLOAD = 3 nF, Figure 3
BST − SW = 4.6 V
BST − SW = 4.6 V
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
CLOAD = 3 nF, Figure 4
BST − SW = 4.6 V
ICC + IBST, IN = 0 V or 5 V
ICC + IBST, SD = 0 V
VCC rising
VCC falling
Min Typ Max
2.0
0.8
−1
+1
20
1.7 3.3
0.8 2.3
14 35
11 25
15 32 70
28 60
1.7 3.3
0.8 2.3
13 30
11 25
25 48
16 30
150 350 600
1
4.6
6
0.8 1.5
325 600
3.8 4.25 4.5
50 120
1 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%.
2 The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO.
3 Guaranteed by characterization, not production tested.
Unit
V
V
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
mA
µA
V
mV
Rev. A | Page 3 of 16

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