CXP5078 查看數據表（PDF） - Sony Semiconductor

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CXP5078

CMOS 4-bit Single Chip Microcomputer

Sony Semiconductor 

CXP5076/5078

∗1 The PC, PD, PG and PH show when the combined pins are selected as the port, and SEG16 to SEG31

show when the combined pins are selected as the segment output.

∗2 It is when the respective pins of PA to PI, PX0 and PX1 select the tri-state output circuit, and PY0 and PY1

are when the inverter output circuit is selected.

∗3 It is when the respective pins of PA to PI, PX0, PX1, PY0 and PY1 select the pull-up resistor.

∗4 The TEX pin specifies the input current when the crystal oscillation is selected by the mask option, and

specifies the leakage current when the schmitt input is selected.

∗5 The RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

when non-resistor is selected.

∗6 The respective pins of PA, PB, PE, PF, PI, PX0 and PX1 specify the input current when the pull-up resistor

is selected, and specify the leakage current when the port state during using the tri-state output circuit or

standby is selected at high impedance.

∗7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistor is selected, and

specify the leakage current when the port state during standby is selected at high impedance.

∗8 The respective pins of PX2, PY2, PY3, INT and RMC only specify the leakage current.

AC characteristics

(1) Clock timing

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Pin

Condition

Min. Typ. Max. Unit

System clock frequency fc

XTAL

EXTAL

Fig. 1, Fig. 2

1

5 MHz

System clock input pulse tXL

width

tXH

System clock input rising tCR

and falling times

tCF

System clock frequency fCS

Event count clock input tEL

pulse width

tEH

EXTAL

TEX∗2

TX

EC

Fig. 1, Fig. 2

(External clock drive)

VDD = 2.5 to 5.5V

Fig. 3

Fig. 4

90

ns

200 ns

32.768

kHz

tsys∗1

+ 0.05

µs

Event count clock input tER

rising and falling times tEF

EC

Fig. 4

20 ms

Event count input clock tTL

input pulse width

tTH

TEX∗3

Fig. 4

10

µs

Event count input clock tTR

rising and falling times tTF

TEX∗3

Fig. 4

20 ms

∗1 tsys in the EXTAL input clock is 8/fc.

tsys in the TEX input clock is 4/fcs.

∗2 Specified when the crystal oscillation mode is selected by the mask option.

∗3 Specified when the counter mode is selected by the mask option.

Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2.

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