SL23EP08 查看數據表（PDF） - Silicon Laboratories
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SL23EP08 Datasheet PDF : 15 Pages
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SL23EP08
Pin Configuration
CLKIN 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
16 FBK
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
16-Pin SOIC and TSSOP
Pin Description
Pin Pin Name
Number
1
CLKIN
2
CLKA1
3
CLKA2
4
VDD
5
GND
6
CLKB1
7
CLKB2
8
S2
9
S1
10
CLKB3
11
CLKB4
12
GND
13
VDD
14
CLKA3
15
CLKA4
16
FBK
Pin Type
Pin Description
Input
Output
Output
Power
Power
Output
Output
Input
Input
Output
Output
Power
Power
Output
Output
Output
Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
3.3V or 2.5V Power Supply.
Power Ground.
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Select Input, select pin S2. Weak pull-up (250kΩ).
Select Input, select pin S1. Weak pull-up (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Buffered Clock Output, Bank B. Weak pull-down (250kΩ).
Power Ground.
3.3V or 2.5V Power Supply.
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
Buffered Clock Output, Bank A. Weak pull-down (250kΩ).
PLL Feedback input.
Rev 1.0, May 18, 2006
Page 2 of 15
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