HSP50415 查看數據表（PDF） - Renesas Electronics
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HSP50415 Datasheet PDF : 29 Pages
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HSP50415
A MATLAB or Excel program for calculating the component
values is available. For improved APLL performance,
utilization of specific calculated values is recommended over
the general purpose ones shown in Figure 1.
Symbol NCO
As the data flows through the device, the sample rate
increases up to the final sample rate, with the SYMBOL
NCO generating all of the necessary intermediate sample
rate clocks. Each stage’s input and output sample rate is
dependent on the interpolation rate through the stage.
Figure 1 shows the various symbol clocks that are generated
on the chip. The symbol rate clock (symclk) used internally is
multiplied by 2 and output on pin 2XSYMCLK for use in
driving the input DATACLK if a symbol rate synchronous
(non-burst) mode is required.
SYSCLK/2
2
The SYMBOL NCO is a 32-bit accumulator. The 32-bit
frequency step (Phinc) is the sum of the user programmable
32-bit symbol Phinc and any error term generated by the
Digital Phase Lock Loop (DPLL) while locking to an external
symbol rate. The DPLL error term may be disabled by a
control bit. The symbol rates supported are from 0.023Hz up
to 25MHz (for FSout of 100MHz) with 32-bit frequency
resolution. The formula for programming the symbol Phinc
register is given as:
symbolPhinc = (symbolRate / FSout) * 2^32
The SYMBOL NCO also has a counter mode in which the
symbol clocks are generated upon the counter reaching the
16-bit user programmable rollover count value. This mode is
useful for cases where the frequency is an integer number of
the system clock (SYSCLK/2).
sysclk
BYPASS
APLL
SELECTOR
CLK
DIN<15:0>
DATACLK
DATA I
INTERFACE
FIFO Q
CONST.
MAP
INT.
COMPLEX
X
12-BIT
FILTER
MIXER
SIN(X)
DAC
FIR
HALFBAND
I GAIN
I GAIN I OFFSET
2XSYMCLK
X2
symclk
(symbol rate)
(symbol rate X 1,2,4,8,16,32)
PLLRC
R1
Internal IC signal names are shown in lowercase.
SYMBOL NCO
C1 C2
DC TO 20MHz: C1=690PF, C2=11NF, R1=120
20 TO 100MHz: C1=130PF, C2=2NF, R1=620
IOUTA
IOUTB
FIGURE 1. SAMPLE RATE CLK GENERATION
TABLE 1. HSP50415 FILTER CONFIGURATIONS AND RESULTING SYMBOL NCO RATES
BYPASS FIR FILTER
FIR INTERPOLATION
BYPASS HALFBAND
FILTER
INTERPOLATING FILTER
DATA INPUT RATE
SYMBOL NCO PHINC
0
x2 (Note)
0
Symbol Rate x 4
PhincLL x 4
0
x4
0
Symbol Rate x 8
PhincLL x 8
0
x8
0
Symbol Rate x 16
PhincLL x 16
0
x16
0
Symbol Rate x 32
PhincLL x 32
0
x2 (Note)
1
Symbol Rate x 4
PhincLL x 4
0
x4
1
Symbol Rate x 4
PhincLL x 4
0
x8
1
Symbol Rate x 8
PhincLL x 8
0
x16
1
Symbol Rate x 16
PhincLL x 16
1
Not applicable
0
Symbol Rate x 2
PhincLL x 2
1
Not applicable
1
Symbol Rate x 1
PhincLL x 1
NOTE: An optional decimate by two mode allows the device to achieve interpolation by a factor of two in the Shaping FIR.
FN4559 Rev 6.00
Apr 23, 2007
Page 6 of 29
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