ISL6532B 查看數據表（PDF） - Renesas Electronics
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ISL6532B Datasheet PDF : 15 Pages
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ISL6532B
LGATE (Pin 19)
LGATE drives the lower (synchronous) FET of the VDDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
FB (Pin 11) and COMP (Pin 12)
The VDDQ switching regulator employs a single voltage control
loop. FB is the negative input to the voltage loop error
amplifier. The positive input of the error amplifier is connected
to a precision 0.8V reference and the output of the error
amplifier is connected to the COMP pin. The VDDQ output
voltage is set by an external resistor divider connected to FB.
With a properly selected divider, VDDQ can be set to any
voltage between the power rail (reduced by converter losses)
and the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP and FB.
The FB pin is also monitored for under and over-voltage
events.
VDDQ (Pins 5, 6)
The VDDQ pins should be connected externally together to the
regulated VDDQ output. During S0/S1 states, the VDDQ pins
serve as inputs to the VTT regulator and to the VTT Reference
precision divider. During S3 (Suspend to RAM) state, the
VDDQ pins serve as an output from the integrated standby
LDO.
VTT (Pins 3, 4)
The VTT pins should be connected together. During S0/S1
states, the VTT pins serve as the outputs of the VTT linear
regulator. During any sleep state, the VTT regulator is disabled.
VTTSNS (Pin 7)
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_OUT (Pin 9)
VREF_OUT is a buffered version of VTT and also acts as the
reference voltage for the VTT linear regulator. It is
recommended that a minimum capacitance of 0.1F be
connected between VDDQ and VREF_OUT and also between
VREF_OUT and GND for proper operation.
VREF_IN (Pin 10)
A capacitor, CSS, connected between VREF_IN and ground is
required. This capacitor and the parallel combination of the
Upper and Lower Divider Impedance (RU||RL), sets the time
constant for the start up ramp when transitioning from S3 to
S0/S1/S2.
The minimum value for CSS can be found through the following
equation:
CSS C--1---V-0---T----T-2--O-A----U----T-R-----U--V----D---R-D---L-Q---
The calculated capacitance, CSS, will charge the output
capacitor bank on the VTT rail in a controlled manner without
reaching the current limit of the VTT LDO.
NCH (Pin 15)
NCH is an open-drain output that controls the MOSFET
blocking backfeed from VDDQ to the input rail during sleep
states. A 2k or larger resistor is to be tied between the 12V
rail and the NCH pin. Until the voltage on the NCH pin reaches
the NCH trip level, the PWM is disabled.
If NCH is not actively utilized, it still must be tied to the 12V rail
through a resistor. For systems using 5V dual as the input to
the switching regulator, a time constant, in the form of a
capacitor, can be added to the NCH pad to delay start of the
PWM switcher until the 5V dual has switched from 5VSBY to
5VATX.
PGOOD (Power Good) (Pin 14)
Power Good is an open-drain logic output that changes to a
logic low if the VTT regulator is out of regulation in S0/S1/S2
state. PGOOD will always be low in any state other than
S0/S1/S2.
S5# (Pin 17)
This pin accepts the SLP_S5# sleep state signal.
S3# (Pin 16)
This pin accepts the SLP_S3# sleep state signal.
Functional Description
Overview
The ISL6532B provides complete control, drive, protection and
ACPI compliance for a regulator powering DDR memory
systems. It is primarily designed for computer applications
powered from an ATX power supply. A 250kHz Synchronous
Buck Regulator with a precision 0.8V reference provides the
proper Core voltage to the system memory of the computer. An
internal LDO regulator with the ability to both sink and source
current and an externally available buffered reference that
tracks the VDDQ output by 50% provides the VTT termination
voltage.
ACPI compliance is realized through the SLP_S3 and SLP_S5
sleep signals and through monitoring of the 12V ATX bus.
Initialization
The ISL6532B automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors the
bias voltage at the 5VSBY and P12V pins. The POR function
initiates soft-start operation after the bias supply voltages
exceed their POR thresholds.
FN9120 Rev 3.00
Jul 2004
Page 7 of 15
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