ISL6532B 查看數據表（PDF） - Renesas Electronics

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ISL6532B

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Renesas Electronics 

ISL6532B

ACPI State Transitions

Cold Start (S5/S4 to S0 Transition)

At the onset of a mechanical start, the ISL6532B receives it’s

bias voltage from the 5V Standby bus (5VSBY). As soon as the

SLP_S3 and SLP_S5 signals have transitioned HIGH, the

ISL6532B starts an internal counter. Following a cold start or

any subsequent S5 state, state transitions are ignored until the

system enters S0/S1. None of the regulators will begin the soft

start procedure until the 5V Standby bus has exceeded POR,

the 12V bus has exceeded POR and VNCH has exceeded the

trip level.

Once all of these conditions are met, the PWM error amplifier

will first be reset by internally shorting the COMP pin to the FB

pin. This reset lasts for 2048 clock cycles which is typically

8.2ms (one clock cycle = 1/fOSC). The digital soft start

sequence will then begin.

The PWM error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). The internal

VTT LDO will also soft start through the reference that tracks

the output of the PWM regulator. The soft start lasts for 2048

clock cycles, which is typically 8.2ms. This method provides a

rapid and controlled output voltage rise.

Figure 1 shows the soft start sequence for a typical cold start.

Due to the soft start capacitance, CSS, on the VREF_IN pin,

the S5 to S0 transition profile of the VTT rail will have a more

rounded features at the start and end of the soft start whereas

the VDDQ profile has distinct starting and ending points to the

ramp up.

S3

S5

12VATX 2V/DIV

5VSBY

1V/DIV

VDDQ

500mV/DIV

VTT

500mV/DIV

PGOOD

5V/DIV

2048 CLOCK 2048 CLOCK

CYCLES

CYCLES

12V POR

SOFT START SOFT START ENDS

INITIATES PGOOD COMPARATOR

ENABLED

FIGURE 1. TYPICAL COLD START

By directly monitoring 12VATX and the SLP_S3 and SLP_S5

signals, the ISL6532B can achieve PGOOD status significantly

faster than other devices that depend on the

Latched_Backfeed_Cut signal for timing.

Active to Sleep (S0 to S3 Transition)

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

ISL6532B will disable the VTT linear regulator. The VDDQ

standby regulator will be enabled and the VDDQ switching

regulator will be disabled. NCH is pulled low to disable the

backfeed blocking MOSFET. PGOOD will also transition LOW.

When VTT is disabled, the internal reference for the VTT

regulator is internally shorted to the VTT rail. This allows the

VTT rail to float. When floating, the voltage on the VTT rail will

depend on the leakage characteristics of the memory and

MCH I/O pins. It is important to note that the VTT rail may not

bleed down to 0V.

The VDDQ rail will be supported in the S3 state through the

standby VDDQ LDO. When S3 transitions LOW, the Standby

regulator is immediately enabled. The switching regulator is

disabled synchronous to the switching waveform. The shut off

time will range between 4 and 8s. The standby LDO is

capable of supporting up to 650mA of load with P5VSBY tied

to the 5V Standby Rail. The standby LDO may receive input

from either the 3.3V Standby rail or the 5V Standby rail through

the P5VSBY pin. It is recommended that the 5V Standby rail

be used as the current delivery capability of the LDO is greater.

Sleep to Active (S3 to S0 Transition)

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the ISL6532B

will enable the VDDQ switching regulator, disable the VDDQ

standby regulator, enable the VTT LDO and force the NCH pin

to a high impedance state turning on the blocking MOSFET.

The internal short between the VTT reference and the VTT rail

is released. Upon release of the short, the capacitor on

VREF_IN is then charged up through the internal resistor

divider network. The VTT output will follow this capacitor

charge-up, acting as the S3 to S0 transition soft start for the

VTT rail. The PGOOD comparator is enabled only after 2048

clock cycles, or typically 8.2ms, have passed following the S3

transition to a HIGH state.

Figure 2 illustrates a typical state transition from S3 to S0. It

should be noted that the soft start profile of the VTT LDO

output will vary according to the value of the capacitor on the

VREF_IN pin.

Active to Shutdown (S0 to S4/S5 Transition)

When the system transitions from active, S0, state to

shutdown, S4/S5, state, the ISL6532B IC disables all

regulators and forces the PGOOD pin and the NCH pin LOW.

VTT Over Current Protection

The internal VTT LDO is protected from fault conditions

through a 3.3A current limit. This current limit protects the

ISL6532B if the LDO is sinking or sourcing current. During an

FN9120 Rev 3.00

Jul 2004

Page 8 of 15

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