EVAL-AD7923CB 查看數據表（PDF） - Analog Devices
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EVAL-AD7923CB Datasheet PDF : 20 Pages
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AD7923
TIMING SPECIFICATIONS1
(AVDD = 2.7 V to 5.25 V, VDRIVE Յ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
fSCLK2
tCONVERT
tQUIET
t2
t33
t43
t5
t6
t7
t84
t9
t10
t11
t12
Limit at TMIN, TMAX AD7923
AVDD = 3 V
AVDD = 5 V
Unit
10
20
16 ¥ tSCLK
50
10
20
16 ¥ tSCLK
50
kHz min
MHz max
ns min
10
35
40
0.4 ¥ tSCLK
0.4 ¥ tSCLK
10
15/45
10
5
20
1
10
30
40
0.4 ¥ tSCLK
0.4 ¥ tSCLK
10
15/35
10
5
20
1
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
ms max
Description
Minimum Quiet Time Required between CS Rising
Edge and Start of Next Conversion
CS to SCLK Setup Time
Delay from CS until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to CS High
Power-Up Time from Full Power-Down/Auto
Shutdown Mode
NOTES
1Sample tested at 25∞C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ VDRIVE.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t 8, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
1.6V
200A
IOH
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
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