EVAL-AD7923CB 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

EVAL-AD7923CB

4-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 16-Lead TSSOP

Analog Devices 

1.0

0.8

AVDD = V DRIVE = 5V

TEMP = 25؇C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

TPC 6. Typical INL

AD7923

1.0

AVDD = V DRIVE = 5V

0.8 TEMP = 25؇C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

512 1024 1536 2048 2560 3072 3584 4096

CODE

TPC 7. Typical DNL

CONTROL REGISTER

The Control Register on the AD7923 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7923 on the falling

edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data

transferred on the DIN line corresponds to the AD7923 configuration for the next conversion. This requires 16 serial clocks for every

data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register.

MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.

MSB

WRITE

Table I. Control Register Bit Functions

SEQ1 DONTC DONTC ADD1 ADD0 PM1 PM0 SEQ0 DONTC RANGE

LSB

CODING

Bit Mnemonic Comment

11 WRITE

The value written to this bit of the Control Register determines whether the following 11 bits will be

loaded to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register;

if it is a 0, the remaining 11 bits are not loaded to the Control Register and it remains unchanged.

10 SEQ1

The SEQ1 bit in the Control Register is used in conjunction with the SEQ0 bit to control the use of the

sequencer function. (See Table IV.)

9–8 DONTC

Don’t Care

7–6 ADD1, ADD0 These two address bits are loaded at the end of the present conversion and select which analog input channel is to

be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described

in Table IV. The selected input channel is decoded as shown in Table II. The address bits corresponding to

the conversion result are also output on DOUT prior to the 12 bits of data. (See the Serial Interface section.)

The next channel to be converted on will be selected by the mux on the 14th SCLK falling edge.

5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7923 as shown in Table III.

3

SEQ0

The SEQ0 bit in the Control Register is used in conjunction with the SEQ1 bit to control the use of the

sequencer function. (See Table IV.)

2

DONTC

Don’t Care

1

RANGE

This bit selects the analog input range to be used on the AD7923. If it is set to 0, the analog input range

will extend from 0 V to 2 ¥ REFIN. If it is set to 1, the analog input range will extend from 0 V to REFIN (for

the next conversion). For the 0 V to 2 ¥ REFIN range, AVDD = 4.75 V to 5.25 V.

0

CODING

This bit selects the type of output coding the AD7923 will use for the conversion result. If this bit is set to 0,

the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the

part will be straight binary (for the next conversion).

REV. 0

–9–

Share Link: