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ADT7301ARTZ-REEL7(RevB) 查看數據表(PDF) - Analog Devices

零件编号
产品描述 (功能)
比赛名单
ADT7301ARTZ-REEL7
(Rev.:RevB)
ADI
Analog Devices ADI
ADT7301ARTZ-REEL7 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADT7301
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD)
and timed from a voltage level of 1.6 V. TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter1
Limit
Unit
Comments
t1
5
ns min
CS to SCLK setup time
t2
25
ns min
SCLK high pulse width
t3
25
ns min
SCLK low pulse width
t4 2
35
ns max
Data access time after SCLK falling edge
t5
20
ns min
Data setup time prior to SCLK rising edge
t6
5
ns min
Data hold time after SCLK rising edge
t7
5
ns min
CS to SCLK hold time
t82
40
ns max
CS to DOUT high Impedance
1 See Figure 14 for the SPI timing diagram.
2 Measured with the load circuit of Figure 2.
200µA
IOL
TO
OUTPUT
PIN CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time
Rev. B | Page 4 of 16

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