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HMC561 查看數據表(PDF) - Analog Devices

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HMC561 Datasheet PDF : 6 Pages
1 2 3 4 5 6
Typical Applications
The HMC561 is suitable for:
• Clock Generation Applications:
SONET OC-192 & SDH STM-64
• Point-to-Point & VSAT Radios
• Test Instrumentation
• Military & Space
Functional Diagram
HMC561
v04.0714
GaAs MMIC x2 ACTIVE FREQUENCY
MULTIPLIER, 8 - 21 GHz OUTPUT
Features
High Output Power: +17 dBm
Low Input Power Drive: 0 to +6 dBm
Fo Isolation: 15 dBc @ Fout= 16 GHz
100 KHz SSB Phase Noise: -139 dBc/Hz
Die Size: 1.6 x 0.9 x 0.1 mm
General Description
The HMC561 is a x2 active broadband frequency
multiplier chip utilizing GaAs PHEMT technology.
When driven by a +5 dBm signal, the multiplier pro-
vides +17 dBm typical output power from 8 to 21 GHz
and the Fo and 3Fo isolations are 15 dBc at 16 GHz.
The HMC561 is ideal for use in LO multiplier chains
for Pt to Pt & VSAT Radios yielding reduced parts
count vs. traditional approaches. The low additive
SSB Phase Noise of -139 dBc/Hz at 100 kHz offset
helps maintain good system noise performance.
Electrical Specifications, TA = +25°C, Vdd1 = Vdd2 = +5V, 5 dBm Drive Level [1]
Parameter
Frequency Range, Input
Frequency Range, Output
Output Power
Fo Isolation (with respect to output level)
3Fo Isolation (with respect to output level)
4Fo Isolation (with respect to output level)
Input Return Loss
Output Return Loss
SSB Phase Noise (100 kHz Offset)
Supply Current (Idd) (Vdd1= Vdd2= +5V, Vgg = -1.7V Typ.)
Min.
Typ.
Max.
4 - 10.5
8 - 21
14
17
15
15
15
15
12
-139
98
126
[1] Adjust Vgg between -2.0 and -1.2V to achieve Idd1 + Idd2 = 98 mA.
Units
GHz
GHz
dBm
dBc
dBc
dBc
dB
dB
dBc/Hz
mA
1
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