CY7C1464AV33(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1464AV33
(Rev.:2004)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Pin Configurations (continued)

209-Ball PBGA

CY7C1464AV33 (512K x 72)

1

2

3

4

5

6

7

A DQg

DQg

A

CE2

A

ADV/LD A

B

DQg DQg

BWSc BWSg NC

WE

A

C

DQg DQg

BWSh BWSd NC

CE1

NC

D

DQg

DQg

VSS

NC

NC

OE

NC

E

DQPg DQPc VDDQ VDDQ VDD

VDD

VDD

F

DQc

DQc

VSS

VSS

VSS

NC

VSS

G

DQc

DQc

VDDQ VDDQ

VDD

NC

VDD

H

DQc

DQc

VSS

VSS

VSS

NC

VSS

J

DQc

DQc

VDDQ VDDQ

VDD

NC

VDD

K

NC

NC

CLK

NC

VSS

CEN

VSS

L

DQh

DQh VDDQ

VDDQ

VDD

NC

VDD

M

DQh

DQh VSS

VSS

VSS

NC

VSS

N

DQh

DQh VDDQ

VDDQ

VDD

NC

VDD

P

DQh DQh VSS

VSS

VSS

ZZ

VSS

R

DQPd DQPh VDDQ VDDQ

VDD

VDD

VDD

T

DQd DQd VSS

NC

NC

MODE NC

U

DQd DQd NC

A

NC/72M A

A

V

DQd DQd

A

A

A

A1

A

W

DQd DQd TMS

TDI

A

A0

A

8

9

10

11

CE3

BWSb

BWSe

NC

VDDQ

VSS

VDDQ

VSS

VDDQ

NC

VDDQ

VSS

VDDQ

VSS

VDDQ

NC

A

A

TDO

A

DQb

BWSf DQb

BWSa DQb

VSS

VDDQ

VSS

DQb

DQPf

DQf

VDDQ

VSS

DQf

DQf

VDDQ

DQf

NC

NC

VDDQ

VSS

VDDQ

DQa

DQa

DQa

VSS

VDDQ

VSS

NC

A

TCK

DQa

DQPa

DQe

DQe

DQe

DQe

DQb

DQb

DQb

DQb

DQPb

DQf

DQf

DQf

DQf

NC

DQa

DQa

DQa

DQa

DQPe

DQe

DQe

DQe

DQe

Pin Definitions

Pin Name

A0

A1

A

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

WE

ADV/LD

I/O Type

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Pin Description

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

Document #: 38-05353 Rev. *A

Page 5 of 27

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