CY7C1464AV33(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1464AV33
(Rev.:2004)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Truth Table[1, 2, 3, 4, 5, 6, 7]

Address

Operation

Used CE ZZ ADV/LD WE BWx OE CEN CLK

DQ

IGNORE CLOCK Current

XL

X

X XX H

L-H

-

EDGE

(Stall)

SLEEP MODE

None

XH

X

X XX X

X

Tri-State

Notes:

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BWX. See Write Cycle Description table for details.

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE is

inactive or when the device is deselected, and DQs=data when OE is active.

Document #: 38-05353 Rev. *A

Page 9 of 27

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