CY7C1471V33(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1471V33
(Rev.:2004)

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1471V33

CY7C1473V33

CY7C1475V33

Pin Definitions

Name

I/O

Description

A0, A1, A

BWA, BWB, BWC,

BWD, BWE, BWF,

BWG, BWH

WE

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge

of the CLK. A[1:0] are fed to the two-bit burst counter.

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When

LOW, a new address can be loaded into the device for an access. After being deselected,

ADV/LD should be driven LOW in order to load a new address.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

Clock

CEN. CLK is only recognized if CEN is active LOW.

CE1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE2, and CE3 to select/deselect the device.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE1 and CE3 to select/deselect the device.

CE3

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE1 and CE2 to select/deselect the device.

OE

Input-

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic

Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are

allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

input data pins. OE is masked during the data portion of a write sequence, during the first

clock when emerging from a deselected state, when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by

the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN

does not deselect the device, CEN can be used to extend the previous cycle when required.

ZZ

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous condition with data integrity preserved. During normal operation, this pin can be connected

to Vss or left floating.

DQs

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The

outputs are automatically tri-stated during the data portion of a write sequence, during the

first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

DQPX

MODE

I/O-

Synchronous

Input Strap Pin

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During

write sequences, DQPX is controlled by BWX correspondingly.

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects

interleaved burst sequence.

VDD

VDDQ

VSS

TDO

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground

Ground for the device.

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

Synchronous JTAG feature is not being utilized, this pin should be left unconnected. This pin is not

available on TQFP packages.

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up

resistor. This pin is not available on TQFP packages.

Document #: 38-05288 Rev. *E

Page 8 of 29

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