NE5751N 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

比赛名单

NE5751N

Audio processor - filter and control section

Philips Electronics 

Philips Semiconductors

Audio processor - filter and control section

Product specification

NE/SA5751

AC ELECTRICAL CHARACTERISTICS (continued)

SYMBOL

PARAMETER

TX BPF noise

TX LPF gain

TX LPF gain with pre-emphasis

TX LPF gain with pre-emphasis

TX LPF gain with pre-emphasis

TX LPF gain with pre-emphasis

TX LPF gain with pre-emphasis

TX LPF gain with pre-emphasis

TX overall gain

TX overall gain

TX overall gain

TX overall gain

TX overall gain

TX BPF output impedance

TX BPF output swing (1%THD)

TX BPF dynamic range

PREMPIN input impedance

Summing op amp

Slew rate

Output impedance

Output swing (1% THD)

Volume control accuracy

Analog switches

Insertion loss

On time transition

Off time transition

TEST CONDITIONS

MIN

300 - 3000kHz

f = 5.9kHz

f = 1kHz, 20dBV

f = 100Hz

f = 300Hz

f = 3kHz

f = 5900Hz

f = 9kHz

1kHz

11.3

100Hz

300Hz

-11

3kHz

8

5.9kHz

f = 1kHz

50kΩ to VREF

f = 1kHz

f = 3kHz

CL = 15pF

Unity gain; f = 3kHz

1kHz, 5kΩ load (25°C)

-30dB to 0dB

-1

MUTET, MUTER

0.8V ->2.0V

MUTET, MUTER

2.0V ->0.8V

LIMITS

TYP

90

-39

12.06

-19

-10.45

9.14

-39

-51

11.8

-47

-10.4

9

-52

360

4.5

90

500

0.75

40

4.3

0

60

3

0.25

MAX

-36

12.5

-45

-9

9.6

-45

UNIT

µVRMS

dB

dB

dBm0

dBm0

dBm0

dBm0

dBm0

dB

dBm0

dBm0

dBm0

dBm0

Ω

VP-P

dB

kΩ

V/µs

Ω

VP-P

+1

dB

dB

µs

µs

I2C CHARACTERISTICS

The I2C bus is for 2-way, 2-line communication between different

ICs or modules. The two lines are a serial data line (SDA) and a

serial clock line (SCL). Both SDA and SCL are bidirectional lines

connected to a positive supply voltage via a pull-up resistor. When

the bus is free, both lines are high. Data transfer may be initiated

only when the bus is not busy.

The output devices, or stages, connected to the bus must have an

open drain or open collector output in order to perform the

wired-AND function.

Data at the I2C bus can be transferred at a rate up to 100kbits/s.

The number of devices connected to the bus is solely dependent on

the maximum allowed bus capacitance of 400pF.

Due to the variety of different devices which can be connected to

the I2C bus, the levels of the logical “0” and “1” are not fixed and

depend on the appropriate level of VDD. For the typical supply

voltage of 5V which is chosen here, logical “1” and logical “0” are,

however, fixed respectively on maximum input LOW voltage, 1.5V

and minimum input HIGH voltage, 3.0V.

BIT TRANSFER

One data bit is transferred during each clock pulse. The data on the

SDA line must remain stable during the HIGH period of the clock’s

cycle. If it does not remain HIGH, it may be interrupted as a control

signal.

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A

HIGH to LOW transition of the data line while the clock line is HIGH

is defined as a start condition S. A LOW to HIGH transition of the

data line while the clock is HIGH is defined as a stop condition.

1990 Aug 17

1055

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