NE5751N 查看數據表（PDF） - Philips Electronics

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NE5751N

Audio processor - filter and control section

Philips Electronics 

Philips Semiconductors

Audio processor - filter and control section

Product specification

NE/SA5751

SYSTEM CONFIGURATIONS

A device generating a message is a “transmitter”; a device receiving

a message is the “receiver”. The device that controls the message

is the “master”; and devices which are controlled by the master are

the “slaves”.

ACKNOWLEDGE

The number of data bytes transferred between the start and the stop

condition from transmitter to receiver is not limited. Each byte of

eight bits is followed by one acknowledge bit. The acknowledge bit

is a HIGH level put on the bus by the transmitter whereas the

master generates an extra acknowledge related clock pulse. A

slave receiver which is addressed must generate an acknowledge

after the reception of each byte that has been clocked out of the

slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the acknowledge

related clock pulse; set up and hold times must be taken into

account.

I2C BUS DATA CONFIGURATIONS

The NE5751 is always a slave receiver in the I2C bus configuration

(R/W bit-0). The slave address consists of seven bits in the serial

mode where the least significant bit is selectable by hardware on

input A0 and the other more significant bits are internally fixed.

POWER ON RESET

In order to avoid undefined states of the NE5751 when the power is

switched on, a power on reset is supplied. The reset is active when

Pin VREF is held below 0.8V. The reset is off when Pin VREF is

above 2.0V. Pin VREF is normally at 2.5V generated by a resistive

divider from VDD. Nominal impedance is 20kΩ. In a typical

application a capacitor is connected to Pin VREF to improve power

supply rejection. The time delay of the network resets the internal

registers when power is first applied. The signal paths are off in the

reset condition. The NE5751 must be programmed via the I2C bus

for normal operation. The Power Down mode is defined only when

all register values are zero.

CONTROL REGISTERS

Register Map

The address register is as follows:

MSB

A6 A5 A4 A3 A2 A1

1

00000

LSB

A0 R/W

SA1 0

SA1 is controlled by serial bus address pin.

Signal Path Register

MSB

LSB

T10 T9 T8 T6 VOXEN T4 T3T5 T2

T2

is the transmission gate between Pin PREEMPIN and the

emphasis input.

T3T5

T4

connects the output of the DTMF generator to the emphasis

input and connects the output of the XMT LPF to

Pin TXDTMFOUT.

connects the output of the XMT LPF to Pin TXLFOUT.

VOXEN enables the VOX function of NE5750.

T6

connects Pin VCIN to the volume control.

T8

connects the output of the DTMF generator to the volume

control.

T9

enables VCOUT1.

T10

enables VCOUT2.

Volume Control and Test Register

MSB

LSB

PDW T1T7 DEE PRE V1 V2 V3 V4

V4

is volume control bit 4. This is the MSB. A zero is 16dB

attenuation.

V3

is volume control bit 3. A zero is 8dB attenuation.

V2

is volume control bit 2. A zero is 4dB attenuation.

V1

is volume control bit 1. A zero is 2dB attenuation.

PRE is the bypass for the pre-emphasis.

DEE is the bypass for the de-emphasis.

T1T7 is the bypass for the compressor and expandor.

PDW is the control for power down mode.

This mode is defined only when all register values are reset to zero.

High Tone DTMF Register

MSB

LSB

HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0

The eight bits determine the output frequency by the following

formula.:

High Frequency = 1200kHz/6/HD

where HD is the value of the register.

Low Tone DTMF Register

MSB

LSB

LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

The eight bits determine the output frequency by the following

formula.:

Low Frequency = 1200kHz/12/LD

where LD is the value of the register.

The operation of the 96ms DTMF timer is initiated by the loading of

the low tone DTMF register. This timer terminates transmission of

the tones as the generated tones cross the reference level after

96ms. The on time of the tones can thus vary by up to one cycle of

the tones.

Continuous tones can be obtained by again loading the two DTMF

registers before 96ms have elapsed.

Single tones can be obtained by loading 0, 1 or 2 into one of the

registers to silence it.

Phase continuous frequency modulation can be produced by loading

a new value into a DTMF register during operation.

1990 Aug 17

1056

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