M34250M2 查看數據表（PDF） - Renesas Electronics

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M34250M2

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 10 Control registers related to timer

Timer control register V1

V13 G1/TOUT pin function selection bit

V12 Prescaler/timer 1 operation start bit

V11 Timer 1 interrupt enable bit

V10 External interrupt enable bit

at reset : 00002

at RAM back-up : 00002

R/W

0 Port G1 (I/O)

1 TOUT pin (output)/port G1(input)

0 Prescaler stop (initial state) / timer 1 stop (state retained)

1 Prescaler / timer 1 operation

0 Interrupt disabled (SNZ1 instruction is valid)

1 Interrupt enabled (SNZ1 instruction is invalid)

0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid)

Key-on wakeup control register K0

K03 Prescaler dividing ratio selection bit

Interrupt valid waveform for INT pin/

K02 key-on wakeup valid waveform selection

bit (Note 2)

at reset : 00002

at RAM back-up : state retained

0 Instruction clock divided by 4

1 Instruction clock divided by 512

0 Rising waveform (“L” → “H”)

R/W

1 Falling waveform (“H” → “L”)

K01 Ports G1–G3 key-on wakeup control bit

0 Key-on wakeup not used

1 Key-on wakeup used (“L” level recognized)

K00 Ports S0–S3 key-on wakeup control bit

0 Key-on wakeup not used

1 Key-on wakeup used (“L” level recognized)

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least

one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when

the interrupt valid waveform is changed.

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