M34250M2 查看數據表（PDF） - Renesas Electronics
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M34250M2 Datasheet PDF : 59 Pages
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MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
The 4250 Group has the RAM back-up mode.
When the POF instruction is executed continuously, system
enters the RAM back-up state.
As oscillation stops retaining RAM, the function of reset circuit
and states at RAM back-up mode, current dissipation can be
reduced without losing the contents of RAM. Table 12 shows
the function and states retained at RAM back-up. Figure 24 shows
the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
(2) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF instruction
continuously, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the software from address 0 in page
0 when reset pulse is input to RESET pin.
In this case, the P flag is “0.”
Table 12 Functions and states retained at RAM back-up
Function
RAM back-up
Program counter (PC), registers A, B,
!
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
O
Port
!
Timer control register V1
!
Timer 1 function
!
Pull-up control register PU0
O
Key-on wakeup control register K0
O
Logic operation selection register LO
!
External interrupt request flag (EXF0)
!
Timer 1 interrupt request flag (T1F)
!
Interrupt enable flag (INTE)
!
Notes 1: “O” represents that the function can be retained, and
“!” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “3” at RAM back-up.
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode. Table 13 shows the return condition for each
return source.
Table 13 Return source and return condition
Return source
G0/INT pin
Ports G1–G3
S0–S3
Return condition
Remarks
Return by an external rising edge Select the return edge (rising edge or falling edge) with the bit 2 of register
input (“L”→“H”) or falling edge K0 according to the external state before going into the RAM back-up
input (“H”→“L”).
state.
The EXF0 flag is not set.
Return by an external “L” level Set the port using the key-on wakeup function selected with register K0
input.
to “H” level before going into the RAM back-up state.
Note: G0/INT pin and ports G1–G3, S0–S3 share the circuit which is used to detect the edge and to recognize “L” level.
The G0/INT pin cannot be set to “no key-on wakeup.”
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