UT52L1616MC-7 查看數據表（PDF） - Utron Technology Inc
零件编号
产品描述 (功能)
比赛名单
UT52L1616MC-7 Datasheet PDF : 36 Pages
| |||
UTRON
Preliminary Rev. 0.91
UT52L1616
1M X 16 BIT SDRAM
CKE Truth Table
Current state
Function
Active
Any
Clock suspend
Clock suspend mode entry
Clock suspend
Clock suspend mode exit
Idle
Auto-refresh command REF
Idle
Self-refresh entry SELF
Idle
Power down entry
Self refresh
Self refresh exit SELFX
Power down
Power down exit
Note: H: VIH. L: VIL. x: VIH or VIL.
CKE CKE
n-1 n
CE
RAS CAS WE
Address
H
L
H
X
X
X
X
L
L
X
X
X
X
X
L
H
L
H
H
H
X
L
H
H
X
X
X
X
H
H
L
L
L
H
X
H
L
L
L
L
H
X
H
L
L
H
H
H
X
H
L
H
X
X
X
X
L
H
L
H
H
H
X
L
H
H
X
X
X
X
L
H
L
H
H
H
X
L
H
H
X
X
X
X
Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown
below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the
bank active status.
READ suspend and READ A suspend: The data being output is held (and continues to be output).
WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the
internal state is held.
Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM
starts auto-refresh operation, (The auto-refresh is the same as the REF refresh of conventional DRAMs.) During
the auto-refresh operation, refresh address and bank select address are generated inside the synchronous DRAM.
For every auto-refresh cycle, the internal address counter is updated. Accordingly, 2048 times are required to
refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state.
In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge
command is required after auto refresh.
Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM starts
self refresh operation. After the execution of this command, self refresh continues while CKE is Low. Since self
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input
circuit.
Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can exit
from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
P90004
Share Link: 